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Searched refs:sqadd (Results 1 – 25 of 65) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dsqadd.s11 sqadd z0.b, z0.b, z0.b label
17 sqadd z0.h, z0.h, z0.h label
23 sqadd z0.s, z0.s, z0.s label
29 sqadd z0.d, z0.d, z0.d label
35 sqadd z0.b, z0.b, #0 label
41 sqadd z31.b, z31.b, #255 label
47 sqadd z0.h, z0.h, #0 label
53 sqadd z0.h, z0.h, #0, lsl #8 label
59 sqadd z31.h, z31.h, #255, lsl #8 label
65 sqadd z31.h, z31.h, #65280 label
[all …]
Dsqadd-diagnostics.s4 sqadd z22.h, z10.h, z32.h label
10 sqadd z20.h, z2.h, z31.x label
16 sqadd z27.h, z11.h, z27.b label
25 sqadd z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b label
30 sqadd z0.b, z0.b, #-1 label
35 sqadd z0.b, z0.b, #1, lsl #8 label
40 sqadd z0.b, z0.b, #256 label
45 sqadd z0.h, z0.h, #-1 label
50 sqadd z0.h, z0.h, #256, lsl #8 label
55 sqadd z0.h, z0.h, #65536 label
[all …]
/external/libhevc/common/arm64/
Dihevc_weighted_pred_bi_default.s199 sqadd v18.4h,v6.4h,v7.4h
200 sqadd v18.4h,v18.4h,v0.4h //vaddq_s32(i4_tmp1_t1, tmp_lvl_shift_t)
202 sqadd v20.4h,v1.4h,v3.4h //vaddq_s32(i4_tmp2_t1, i4_tmp2_t2)
203 sqadd v19.4h,v20.4h,v0.4h //vaddq_s32(i4_tmp2_t1, tmp_lvl_shift_t)
208 sqadd v30.4h,v22.4h,v23.4h
209 sqadd v30.4h,v30.4h,v0.4h //vaddq_s32(i4_tmp1_t1, tmp_lvl_shift_t) iii iteration
212 sqadd v18.4h,v24.4h,v25.4h //vaddq_s32(i4_tmp2_t1, i4_tmp2_t2) iv iteration
213 sqadd v31.4h,v18.4h,v0.4h
254 sqadd v18.4h,v6.4h,v7.4h
255 sqadd v18.4h,v18.4h,v0.4h //vaddq_s32(i4_tmp1_t1, tmp_lvl_shift_t)
[all …]
Dihevc_intra_pred_luma_horz.s215 sqadd v22.8h, v26.8h , v24.8h
229 sqadd v22.8h, v26.8h , v24.8h
297 sqadd v22.8h, v26.8h , v24.8h
341 sqadd v22.8h, v26.8h , v24.8h
Dihevc_intra_pred_luma_vert.s207 sqadd v0.8h, v0.8h , v30.8h
208 sqadd v28.8h, v28.8h , v30.8h
342 sqadd v0.8h, v26.8h , v30.8h
Dihevc_intra_pred_chroma_horz.s300 sqadd v22.8h, v26.8h , v24.8h
344 sqadd v22.8h, v26.8h , v24.8h
/external/capstone/suite/MC/AArch64/
Dneon-saturating-add-sub.s.cs2 0x20,0x0c,0x22,0x0e = sqadd v0.8b, v1.8b, v2.8b
3 0x20,0x0c,0x22,0x4e = sqadd v0.16b, v1.16b, v2.16b
4 0x20,0x0c,0x62,0x0e = sqadd v0.4h, v1.4h, v2.4h
5 0x20,0x0c,0x62,0x4e = sqadd v0.8h, v1.8h, v2.8h
6 0x20,0x0c,0xa2,0x0e = sqadd v0.2s, v1.2s, v2.2s
7 0x20,0x0c,0xa2,0x4e = sqadd v0.4s, v1.4s, v2.4s
8 0x20,0x0c,0xe2,0x4e = sqadd v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s.cs2 0x20,0x0c,0x22,0x5e = sqadd b0, b1, b2
3 0x6a,0x0d,0x6c,0x5e = sqadd h10, h11, h12
4 0xb4,0x0e,0xa2,0x5e = sqadd s20, s21, s2
5 0xf1,0x0f,0xe8,0x5e = sqadd d17, d31, d8
/external/llvm/test/MC/AArch64/
Dneon-saturating-add-sub.s9 sqadd v0.8b, v1.8b, v2.8b
10 sqadd v0.16b, v1.16b, v2.16b
11 sqadd v0.4h, v1.4h, v2.4h
12 sqadd v0.8h, v1.8h, v2.8h
13 sqadd v0.2s, v1.2s, v2.2s
14 sqadd v0.4s, v1.4s, v2.4s
15 sqadd v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s6 sqadd b0, b1, b2
7 sqadd h10, h11, h12
8 sqadd s20, s21, s2
9 sqadd d17, d31, d8
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-saturating-add-sub.s9 sqadd v0.8b, v1.8b, v2.8b
10 sqadd v0.16b, v1.16b, v2.16b
11 sqadd v0.4h, v1.4h, v2.4h
12 sqadd v0.8h, v1.8h, v2.8h
13 sqadd v0.2s, v1.2s, v2.2s
14 sqadd v0.4s, v1.4s, v2.4s
15 sqadd v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s6 sqadd b0, b1, b2
7 sqadd h10, h11, h12
8 sqadd s20, s21, s2
9 sqadd d17, d31, d8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vqadd.ll5 ;CHECK: sqadd.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
14 ;CHECK: sqadd.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
23 ;CHECK: sqadd.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
59 ;CHECK: sqadd.16b
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
68 ;CHECK: sqadd.8h
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
[all …]
Darm64-neon-v8.1a.ll15 declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>)
17 declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>)
18 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
19 declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32)
20 declare i16 @llvm.aarch64.neon.sqadd.i16(i16, i16)
36 %retval = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc, <4 x i16> %prod)
46 %retval = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc, <8 x i16> %prod)
56 %retval = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %acc, <2 x i32> %prod)
66 %retval = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc, <4 x i32> %prod)
[all …]
Darm64-arith-saturating.ll5 ; CHECK: sqadd s0, s0, s1
8 %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
14 ; CHECK: sqadd d0, d0, d1
17 %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
41 declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone
42 declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
Dmachine-copy-prop.ll33 …%sqadd = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %…
34 %shuffle = shufflevector <4 x i32> %sqadd, <4 x i32> undef, <2 x i32> zeroinitializer
99 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
Darm64-detect-vec-redux.ll22 …%vqdmlal_v3.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %vpaddq_v2.i, <2 x i6…
42 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) #1
Darm64-neon-2velem-high.ll274 …%vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.…
286 …%vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.…
300 …%vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i…
312 …%vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i…
573 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
574 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
Darm64-vmul.ll298 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
299 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
310 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
321 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
334 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
347 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
977 %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
990 %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
1004 %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
1018 %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-vqadd.ll5 ;CHECK: sqadd.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
14 ;CHECK: sqadd.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
23 ;CHECK: sqadd.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
59 ;CHECK: sqadd.16b
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
68 ;CHECK: sqadd.8h
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
[all …]
Darm64-neon-v8.1a.ll12 declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>)
13 declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>)
14 declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>)
15 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
16 declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32)
17 declare i16 @llvm.aarch64.neon.sqadd.i16(i16, i16)
33 %retval = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc, <4 x i16> %prod)
43 %retval = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc, <8 x i16> %prod)
53 %retval = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %acc, <2 x i32> %prod)
63 %retval = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc, <4 x i32> %prod)
[all …]
Darm64-arith-saturating.ll5 ; CHECK: sqadd s0, s0, s1
8 %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
14 ; CHECK: sqadd d0, d0, d1
17 %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
41 declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone
42 declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
Dmachine-copy-prop.ll33 …%sqadd = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %…
34 %shuffle = shufflevector <4 x i32> %sqadd, <4 x i32> undef, <2 x i32> zeroinitializer
99 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
Darm64-detect-vec-redux.ll22 …%vqdmlal_v3.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %vpaddq_v2.i, <2 x i6…
42 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) #1
Darm64-neon-2velem-high.ll274 …%vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.…
286 …%vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.…
300 …%vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i…
312 …%vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i…
573 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
574 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)

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