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Searched refs:src0_neg (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_disasm.c54 uint32_t src0_neg : 1; member
548 .neg = instr->src0_neg, in print_instr()
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td96 bits<1> src0_neg;
99 let Word0{12} = src0_neg;
DR600Instructions.td97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
179 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
185 "$src0_neg$src0$src0_rel, "
DR600ExpandSpecialInstrs.cpp342 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg); in runOnMachineFunction()
DVIInstrFormats.td200 let Inst{52} = src0_modifiers{0}; // src0_neg
DR600InstrInfo.cpp1322 OPERAND_CASE(AMDGPU::OpName::src0_neg) in getSlotedOps()
1362 AMDGPU::OpName::src0_neg, in buildSlotOfVectorInstruction()
1451 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_neg); in getFlagOp()
DEvergreenInstructions.td405 let src0_neg = 0;
DR600ISelLowering.cpp2387 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg), in PostISelFolding()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td106 bits<1> src0_neg;
109 let Word0{12} = src0_neg;
DR600ExpandSpecialInstrs.cpp279 SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_neg); in runOnMachineFunction()
DR600Instructions.td108 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
113 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
150 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
156 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
190 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
196 "$src0_neg$src0$src0_rel, "
DR600InstrInfo.cpp1301 OPERAND_CASE(R600::OpName::src0_neg) in getSlotedOps()
1341 R600::OpName::src0_neg, in buildSlotOfVectorInstruction()
1426 FlagIndex = getOperandIdx(MI, R600::OpName::src0_neg); in getFlagOp()
DVOPInstructions.td500 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
DEvergreenInstructions.td479 let src0_neg = 0;
DR600ISelLowering.cpp2274 TII->getOperandIdx(Opcode, R600::OpName::src0_neg), in PostISelFolding()
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_optimize.c584 unsigned src0_neg = inst_add->U.I.SrcReg[0].Negate & dstmask; in peephole_add_presub_add() local
599 if (inst_add->U.I.SrcReg[0].Negate && src0_neg != dstmask) in peephole_add_presub_add()