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Searched refs:src_layout (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cmd_buffer.c42 VkImageLayout src_layout,
3917 VkImageLayout src_layout, in radv_handle_depth_image_transition() argument
3931 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED && in radv_handle_depth_image_transition()
3935 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) && in radv_handle_depth_image_transition()
3939 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) && in radv_handle_depth_image_transition()
3973 VkImageLayout src_layout, in radv_handle_cmask_image_transition() argument
3979 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { in radv_handle_cmask_image_transition()
3984 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) && in radv_handle_cmask_image_transition()
4008 VkImageLayout src_layout, in radv_handle_dcc_image_transition() argument
4014 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) { in radv_handle_dcc_image_transition()
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/external/mesa3d/src/intel/blorp/
Dblorp_priv.h243 enum isl_msaa_layout src_layout; member
Dblorp_blit.c1101 assert(key->tex_layout == key->src_layout); in brw_blorp_build_nir_shader()
1117 assert((key->src_layout == ISL_MSAA_LAYOUT_NONE) == in brw_blorp_build_nir_shader()
1246 key->tex_layout != key->src_layout) { in brw_blorp_build_nir_shader()
1248 key->src_layout); in brw_blorp_build_nir_shader()
1650 wm_prog_key->src_layout = params->src.surf.msaa_layout; in try_blorp_blit()
/external/mesa3d/src/intel/vulkan/
Danv_descriptor_set.c785 const struct anv_descriptor_set_binding_layout *src_layout = in anv_UpdateDescriptorSets() local
788 &src->descriptors[src_layout->descriptor_index]; in anv_UpdateDescriptorSets()