| /external/u-boot/drivers/bios_emulator/x86emu/ |
| D | ops2.c | 327 u32 *srcreg,*shiftreg; in x86emuOp2_bt_R() local
329 srcreg = DECODE_RM_LONG_REGISTER(rl); in x86emuOp2_bt_R()
334 CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); in x86emuOp2_bt_R()
336 u16 *srcreg,*shiftreg; in x86emuOp2_bt_R() local
338 srcreg = DECODE_RM_WORD_REGISTER(rl); in x86emuOp2_bt_R()
343 CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); in x86emuOp2_bt_R()
555 u32 *srcreg,*shiftreg; in x86emuOp2_bts_R() local
558 srcreg = DECODE_RM_LONG_REGISTER(rl); in x86emuOp2_bts_R()
564 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); in x86emuOp2_bts_R()
565 *srcreg |= mask; in x86emuOp2_bts_R()
[all …]
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| D | ops.c | 208 u8 *destreg, *srcreg; in x86emuOp_genop_byte_RM_R() local
221 srcreg = DECODE_RM_BYTE_REGISTER(rh); in x86emuOp_genop_byte_RM_R()
224 destval = genop_byte_operation[op1](destval, *srcreg); in x86emuOp_genop_byte_RM_R()
231 srcreg = DECODE_RM_BYTE_REGISTER(rh); in x86emuOp_genop_byte_RM_R()
234 *destreg = genop_byte_operation[op1](*destreg, *srcreg); in x86emuOp_genop_byte_RM_R()
260 u32 *srcreg; in x86emuOp_genop_word_RM_R() local
264 srcreg = DECODE_RM_LONG_REGISTER(rh); in x86emuOp_genop_word_RM_R()
267 destval = genop_long_operation[op1](destval, *srcreg); in x86emuOp_genop_word_RM_R()
271 u16 *srcreg; in x86emuOp_genop_word_RM_R() local
275 srcreg = DECODE_RM_WORD_REGISTER(rh); in x86emuOp_genop_word_RM_R()
[all …]
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 131 static struct rc_src_register srcreg(int file, int index) in srcreg() function
255 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index)); in transform_CEIL()
271 srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1]); in transform_CLAMP()
320 inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, dst.Index))); in transform_FLR()
336 negate(srcreg(RC_FILE_TEMPORARY, dst.Index))); in transform_TRUNC()
338 negate(srcreg(RC_FILE_TEMPORARY, dst.Index)), srcreg(RC_FILE_TEMPORARY, dst.Index)); in transform_TRUNC()
375 srcreg(RC_FILE_TEMPORARY, rc_find_free_temporary(c))); in transform_LIT()
383 srctemp = srcreg(RC_FILE_TEMPORARY, temp); in transform_LIT()
391 swizzle(srcreg(RC_FILE_CONSTANT, constant), in transform_LIT()
435 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[2]); in transform_LRP()
[all …]
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| D | radeon_compiler_util.c | 288 struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg) in lmul_swizzle() argument
290 struct rc_src_register tmp = srcreg; in lmul_swizzle()
297 tmp.Swizzle |= GET_SWZ(srcreg.Swizzle, swz) << (i*3); in lmul_swizzle()
298 tmp.Negate |= GET_BIT(srcreg.Negate, swz) << i; in lmul_swizzle()
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| D | radeon_compiler_util.h | 73 struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg);
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| /external/mesa3d/src/gallium/drivers/svga/svgadump/ |
| D | svga_shader_dump.c | 417 static void dump_srcreg( struct sh_srcreg srcreg, struct sh_srcreg *indreg, const struct dump_info … in dump_srcreg() argument
422 memcpy(&srcreg_sh, &srcreg, sizeof(srcreg_sh)); in dump_srcreg()
424 switch (srcreg.modifier) { in dump_srcreg()
439 switch (srcreg.modifier) { in dump_srcreg()
470 …if (srcreg.swizzle_x != 0 || srcreg.swizzle_y != 1 || srcreg.swizzle_z != 2 || srcreg.swizzle_w !=… in dump_srcreg()
472 …if (srcreg.swizzle_x == srcreg.swizzle_y && srcreg.swizzle_y == srcreg.swizzle_z && srcreg.swizzle… in dump_srcreg()
473 _debug_printf( "%c", "xyzw"[srcreg.swizzle_x] ); in dump_srcreg()
476 _debug_printf( "%c", "xyzw"[srcreg.swizzle_x] ); in dump_srcreg()
477 _debug_printf( "%c", "xyzw"[srcreg.swizzle_y] ); in dump_srcreg()
478 _debug_printf( "%c", "xyzw"[srcreg.swizzle_z] ); in dump_srcreg()
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_tiled_memcpy.c | 124 __m128i srcreg, dstreg, agmask, ag, rb, br; in rgba8_copy_16_aligned_dst() local
127 srcreg = _mm_loadu_si128((__m128i *)src); in rgba8_copy_16_aligned_dst()
129 rb = _mm_andnot_si128(agmask, srcreg); in rgba8_copy_16_aligned_dst()
130 ag = _mm_and_si128(agmask, srcreg); in rgba8_copy_16_aligned_dst()
141 __m128i srcreg, dstreg, agmask, ag, rb, br; in rgba8_copy_16_aligned_src() local
144 srcreg = _mm_load_si128((__m128i *)src); in rgba8_copy_16_aligned_src()
146 rb = _mm_andnot_si128(agmask, srcreg); in rgba8_copy_16_aligned_src()
147 ag = _mm_and_si128(agmask, srcreg); in rgba8_copy_16_aligned_src()
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| /external/mesa3d/src/gallium/docs/source/drivers/freedreno/ |
| D | ir3-notes.rst | 119 ``foreach_src(srcreg, instr)``
122 ``foreach_src_n(srcreg, n, instr)``
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoD.td | 74 // Operands for stores are in the order srcreg, base, offset rather than
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| D | RISCVInstrInfoF.td | 95 // Operands for stores are in the order srcreg, base, offset rather than
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| D | RISCVInstrInfo.td | 231 // Operands for stores are in the order srcreg, base, offset rather than
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