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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
Dintrinsic-old.ll11 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
13 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
19 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.y(), !range ![[BLK_IDX_XY]]
21 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
27 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]]
29 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
36 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
42 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
44 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
50 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
[all …]
Dbug22322.ll13 %0 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
14 %1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
16 %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
40 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
43 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
46 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
/external/llvm/test/CodeGen/NVPTX/
Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
Dintrinsic-old.ll11 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
13 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
19 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.y(), !range ![[BLK_IDX_XY]]
21 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
27 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]]
29 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
36 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
42 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
44 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
50 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
[all …]
Dbug22322.ll13 %0 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
14 %1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
16 %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
40 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
43 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
46 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/pseudo/
DCPCWRdRr.mir20 ; CHECK: CPCRdRr $r20, $r22, implicit-def $sreg, implicit killed $sreg
21 ; CHECK-NEXT: CPCRdRr $r21, $r23, implicit-def $sreg, implicit killed $sreg
23 CPCWRdRr $r21r20, $r23r22, implicit-def $sreg, implicit $sreg
DSBCIWRdK.mir20 ; CHECK: $r20 = SBCIRdK $r20, 175, implicit-def $sreg, implicit killed $sreg
21 ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
23 $r21r20 = SBCIWRdK $r21r20, 64175, implicit-def $sreg, implicit $sreg
DADCWRdRr.mir20 ; CHECK: $r14 = ADCRdRr $r14, $r20, implicit-def $sreg, implicit $sreg
21 ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = ADCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
DSBCWRdRr.mir20 ; CHECK: $r14 = SBCRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SBCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
DLSLWRd.mir18 ; CHECK: $r14 = LSLRd $r14, implicit-def $sreg
19 ; CHECK-NEXT: $r15 = ROLRd $r15, implicit-def $sreg, implicit killed $sreg
21 $r15r14 = LSLWRd $r15r14, implicit-def $sreg
DLSRWRd.mir18 ; CHECK: $r15 = LSRRd $r15, implicit-def $sreg
19 ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
21 $r15r14 = LSRWRd $r15r14, implicit-def $sreg
DASRWRd.mir18 ; CHECK: $r15 = ASRRd $r15, implicit-def $sreg
19 ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
21 $r15r14 = ASRWRd $r15r14, implicit-def $sreg
DSUBIWRdK.mir20 ; CHECK: $r20 = SUBIRdK $r20, 175, implicit-def $sreg
21 ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
23 $r21r20 = SUBIWRdK $r21r20, 64175, implicit-def $sreg
DZEXT.mir20 ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SEXT $r31, implicit-def $sreg
DADDWRdRr.mir20 ; CHECK: $r14 = ADDRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = ADDWRdRr $r15r14, $r21r20, implicit-def $sreg
DSUBWRdRr.mir20 ; CHECK: $r14 = SUBRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SUBWRdRr $r15r14, $r21r20, implicit-def $sreg
DCPWRdRr.mir20 ; CHECK: CPRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-NEXT: CPCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 CPWRdRr $r15r14, $r21r20, implicit-def $sreg
DSEXT.mir20 ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SEXT $r31, implicit-def $sreg
DANDIWRdK.mir20 ; CHECK: $r16 = ANDIRdK $r16, 175, implicit-def dead $sreg
21 ; CHECK-NEXT: $r17 = ANDIRdK $r17, 250, implicit-def $sreg
23 $r17r16 = ANDIWRdK $r17r16, 64175, implicit-def $sreg
DORIWRdK.mir20 ; CHECK: $r20 = ORIRdK $r20, 175, implicit-def dead $sreg
21 ; CHECK-NEXT: $r21 = ORIRdK $r21, 250, implicit-def $sreg
23 $r21r20 = ORIWRdK $r21r20, 64175, implicit-def $sreg
DCOMWRd.mir20 ; CHECK: $r14 = COMRd $r14, implicit-def dead $sreg
21 ; CHECK-NEXT: $r15 = COMRd $r15, implicit-def $sreg
23 $r15r14 = COMWRd $r15r14, implicit-def $sreg
/external/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
Ddiverge.ll10 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
32 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
53 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
103 %laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
125 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
161 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
192 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
209 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
210 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
Ddiverge.ll10 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
32 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
53 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
103 %laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
125 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
161 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
192 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
209 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
210 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
[all …]
/external/v8/src/arm/
Dsimulator-arm.h128 void set_s_register_from_float(int sreg, const Float32 flt) { in set_s_register_from_float() argument
129 SetVFPRegister<Float32, 1>(sreg, flt); in set_s_register_from_float()
131 void set_s_register_from_float(int sreg, const float flt) { in set_s_register_from_float() argument
132 SetVFPRegister<float, 1>(sreg, flt); in set_s_register_from_float()
135 Float32 get_float_from_s_register(int sreg) { in get_float_from_s_register() argument
136 return GetFromVFPRegister<Float32, 1>(sreg); in get_float_from_s_register()
139 void set_s_register_from_sinteger(int sreg, const int sint) { in set_s_register_from_sinteger() argument
140 SetVFPRegister<int, 1>(sreg, sint); in set_s_register_from_sinteger()
143 int get_sinteger_from_s_register(int sreg) { in get_sinteger_from_s_register() argument
144 return GetFromVFPRegister<int, 1>(sreg); in get_sinteger_from_s_register()

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