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Searched refs:sscreen (Results 1 – 25 of 33) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.c208 si_create_llvm_target_machine(struct si_screen *sscreen) in si_create_llvm_target_machine() argument
211 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) | in si_create_llvm_target_machine()
212 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) | in si_create_llvm_target_machine()
213 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) | in si_create_llvm_target_machine()
214 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0); in si_create_llvm_target_machine()
216 return ac_create_target_machine(sscreen->info.family, tm_options); in si_create_llvm_target_machine()
248 struct si_screen* sscreen = (struct si_screen *)screen; in si_create_context() local
249 struct radeon_winsys *ws = sscreen->ws; in si_create_context()
256 sscreen->record_llvm_ir = true; /* racy but not critical */ in si_create_context()
265 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */ in si_create_context()
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Dsi_get.c55 const char *si_get_family_name(const struct si_screen *sscreen) in si_get_family_name() argument
57 switch (sscreen->info.family) { in si_get_family_name()
82 static bool si_have_tgsi_compute(struct si_screen *sscreen) in si_have_tgsi_compute() argument
86 return (sscreen->info.chip_class >= CIK || in si_have_tgsi_compute()
87 sscreen->info.drm_major == 3 || in si_have_tgsi_compute()
88 (sscreen->info.drm_major == 2 && in si_have_tgsi_compute()
89 sscreen->info.drm_minor >= 45)); in si_have_tgsi_compute()
94 struct si_screen *sscreen = (struct si_screen *)pscreen; in si_get_param() local
200 return !SI_BIG_ENDIAN && sscreen->info.has_userptr; in si_get_param()
203 return (sscreen->info.drm_major == 2 && in si_get_param()
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Dsi_state_shaders.c187 static bool si_shader_cache_insert_shader(struct si_screen *sscreen, in si_shader_cache_insert_shader() argument
196 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary); in si_shader_cache_insert_shader()
204 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary, in si_shader_cache_insert_shader()
210 if (sscreen->disk_shader_cache && insert_into_disk_cache) { in si_shader_cache_insert_shader()
211 disk_cache_compute_key(sscreen->disk_shader_cache, tgsi_binary, in si_shader_cache_insert_shader()
213 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, in si_shader_cache_insert_shader()
220 static bool si_shader_cache_load_shader(struct si_screen *sscreen, in si_shader_cache_load_shader() argument
225 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary); in si_shader_cache_load_shader()
227 if (sscreen->disk_shader_cache) { in si_shader_cache_load_shader()
231 disk_cache_compute_key(sscreen->disk_shader_cache, in si_shader_cache_load_shader()
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Dsi_state_binning.c44 static struct uvec2 si_find_bin_size(struct si_screen *sscreen, in si_find_bin_size() argument
49 util_logbase2_ceil(sscreen->info.num_render_backends / in si_find_bin_size()
50 sscreen->info.max_se); in si_find_bin_size()
51 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se); in si_find_bin_size()
340 struct si_screen *sscreen = sctx->screen; in si_emit_dpbb_state() local
347 if (!sscreen->dpbb_allowed || !blend || !dsa) { in si_emit_dpbb_state()
398 if (sscreen->dfsm_allowed && in si_emit_dpbb_state()
Dsi_state_draw.c325 si_get_init_multi_vgt_param(struct si_screen *sscreen, in si_get_init_multi_vgt_param() argument
344 if ((sscreen->info.family == CHIP_TAHITI || in si_get_init_multi_vgt_param()
345 sscreen->info.family == CHIP_PITCAIRN || in si_get_init_multi_vgt_param()
346 sscreen->info.family == CHIP_BONAIRE) && in si_get_init_multi_vgt_param()
351 if (sscreen->has_distributed_tess) { in si_get_init_multi_vgt_param()
353 if (sscreen->info.chip_class <= VI) in si_get_init_multi_vgt_param()
357 if (sscreen->info.family == CHIP_TONGA || in si_get_init_multi_vgt_param()
358 sscreen->info.family == CHIP_FIJI || in si_get_init_multi_vgt_param()
359 sscreen->info.family == CHIP_POLARIS10 || in si_get_init_multi_vgt_param()
360 sscreen->info.family == CHIP_POLARIS11 || in si_get_init_multi_vgt_param()
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Dsi_shader.h624 si_generate_gs_copy_shader(struct si_screen *sscreen,
628 int si_compile_tgsi_shader(struct si_screen *sscreen,
633 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
639 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
640 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
643 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
Dsi_test_dma.c138 static const char *array_mode_to_string(struct si_screen *sscreen, in array_mode_to_string() argument
141 if (sscreen->info.chip_class >= GFX9) { in array_mode_to_string()
174 void si_test_dma(struct si_screen *sscreen) in si_test_dma() argument
176 struct pipe_screen *screen = &sscreen->b; in si_test_dma()
286 array_mode_to_string(sscreen, &rdst->surface), in si_test_dma()
288 array_mode_to_string(sscreen, &rsrc->surface), bpp); in si_test_dma()
Dsi_pipe.h712 const char *si_get_family_name(const struct si_screen *sscreen);
713 void si_init_screen_get_functions(struct si_screen *sscreen);
729 void si_test_dma(struct si_screen *sscreen);
820 static inline bool si_can_dump_shader(struct si_screen *sscreen, in si_can_dump_shader() argument
823 return sscreen->debug_flags & (1 << processor); in si_can_dump_shader()
826 static inline bool si_extra_shader_checks(struct si_screen *sscreen, in si_extra_shader_checks() argument
829 return (sscreen->debug_flags & DBG(CHECK_IR)) || in si_extra_shader_checks()
830 si_can_dump_shader(sscreen, processor); in si_extra_shader_checks()
Dsi_clear.c36 static void si_alloc_separate_cmask(struct si_screen *sscreen, in si_alloc_separate_cmask() argument
44 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask); in si_alloc_separate_cmask()
49 si_aligned_buffer_create(&sscreen->b, in si_alloc_separate_cmask()
64 p_atomic_inc(&sscreen->compressed_colortex_counter); in si_alloc_separate_cmask()
240 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, in si_set_optimal_micro_tile_mode() argument
248 assert(sscreen->info.chip_class >= GFX9 || in si_set_optimal_micro_tile_mode()
252 if (sscreen->info.chip_class >= GFX9) { in si_set_optimal_micro_tile_mode()
283 } else if (sscreen->info.chip_class >= CIK) { in si_set_optimal_micro_tile_mode()
341 p_atomic_inc(&sscreen->dirty_tex_counter); in si_set_optimal_micro_tile_mode()
Dsi_fence.c303 struct si_screen *sscreen = (struct si_screen*)ctx->screen; in si_create_fence_fd() local
304 struct radeon_winsys *ws = sscreen->ws; in si_create_fence_fd()
309 if (!sscreen->info.has_fence_to_handle) in si_create_fence_fd()
328 struct si_screen *sscreen = (struct si_screen*)screen; in si_fence_get_fd() local
329 struct radeon_winsys *ws = sscreen->ws; in si_fence_get_fd()
333 if (!sscreen->info.has_fence_to_handle) in si_fence_get_fd()
Dsi_shader.c78 struct si_screen *sscreen,
5261 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader) in si_shader_binary_upload() argument
5285 si_aligned_buffer_create(&sscreen->b, in si_shader_binary_upload()
5286 sscreen->cpdma_prefetch_writes_memory ? in si_shader_binary_upload()
5295 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL, in si_shader_binary_upload()
5322 sscreen->ws->buffer_unmap(shader->bo->buf); in si_shader_binary_upload()
5374 static void si_shader_dump_stats(struct si_screen *sscreen, in si_shader_dump_stats() argument
5384 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256; in si_shader_dump_stats()
5388 switch (sscreen->info.family) { in si_shader_dump_stats()
5427 if (sscreen->info.chip_class >= VI) in si_shader_dump_stats()
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Dsi_state.h321 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
373 void si_init_screen_state_functions(struct si_screen *sscreen);
405 bool si_init_shader_cache(struct si_screen *sscreen);
406 void si_destroy_shader_cache(struct si_screen *sscreen);
Dsi_uvd.c112 struct si_screen *sscreen = (struct si_screen*)buf->base.context->screen; in si_uvd_set_dtb() local
115 enum ruvd_surface_type type = (sscreen->info.chip_class >= GFX9) ? in si_uvd_set_dtb()
Dsi_compute.c153 struct si_screen *sscreen = (struct si_screen *)ctx->screen; in si_create_compute_state() local
174 p_atomic_inc(&sscreen->num_shaders_created); in si_create_compute_state()
181 si_can_dump_shader(sscreen, PIPE_SHADER_COMPUTE); in si_create_compute_state()
188 util_queue_add_job(&sscreen->shader_compiler_queue, in si_create_compute_state()
722 struct si_screen *sscreen = sctx->screen; in si_emit_dispatch_packets() local
731 unsigned num_cu_per_se = sscreen->info.num_good_compute_units / in si_emit_dispatch_packets()
732 sscreen->info.max_se; in si_emit_dispatch_packets()
Dsi_state.c394 static void si_blend_check_commutativity(struct si_screen *sscreen, in si_blend_check_commutativity() argument
431 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add)) in si_blend_check_commutativity()
859 struct si_screen *sscreen = ((struct si_context *)ctx)->screen; in si_create_rs_state() local
933 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9)); in si_create_rs_state()
1605 struct si_screen *sscreen = (struct si_screen*)screen; in si_translate_texformat() local
1606 bool enable_compressed_formats = (sscreen->info.drm_major == 2 && in si_translate_texformat()
1607 sscreen->info.drm_minor >= 31) || in si_translate_texformat()
1608 sscreen->info.drm_major == 3; in si_translate_texformat()
1677 (sscreen->info.family == CHIP_STONEY || in si_translate_texformat()
1678 sscreen->info.chip_class >= GFX9)) { in si_translate_texformat()
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/external/mesa3d/src/gallium/drivers/radeon/
Dr600_gpu_load.c79 static void r600_update_mmio_counters(struct si_screen *sscreen, in r600_update_mmio_counters() argument
86 sscreen->ws->read_registers(sscreen->ws, GRBM_STATUS, 1, &value); in r600_update_mmio_counters()
104 if (sscreen->info.chip_class == CIK || sscreen->info.chip_class == VI) { in r600_update_mmio_counters()
106 sscreen->ws->read_registers(sscreen->ws, SRBM_STATUS2, 1, &value); in r600_update_mmio_counters()
112 if (sscreen->info.chip_class >= VI) { in r600_update_mmio_counters()
114 sscreen->ws->read_registers(sscreen->ws, CP_STAT, 1, &value); in r600_update_mmio_counters()
133 struct si_screen *sscreen = (struct si_screen*)param; in r600_gpu_load_thread() local
138 while (!p_atomic_read(&sscreen->gpu_load_stop_thread)) { in r600_gpu_load_thread()
156 r600_update_mmio_counters(sscreen, &sscreen->mmio_counters); in r600_gpu_load_thread()
158 p_atomic_dec(&sscreen->gpu_load_stop_thread); in r600_gpu_load_thread()
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Dr600_texture.c39 static void r600_texture_discard_cmask(struct si_screen *sscreen,
42 r600_choose_tiling(struct si_screen *sscreen,
181 static unsigned r600_texture_get_offset(struct si_screen *sscreen, in r600_texture_get_offset() argument
187 if (sscreen->info.chip_class >= GFX9) { in r600_texture_get_offset()
220 static int r600_init_surface(struct si_screen *sscreen, in r600_init_surface() argument
252 (sscreen->info.chip_class >= GFX9 || in r600_init_surface()
259 if (sscreen->info.chip_class == VI) in r600_init_surface()
269 if (sscreen->info.chip_class >= VI && in r600_init_surface()
274 (!sscreen->dcc_msaa_allowed || ptex->array_size > 1)))) in r600_init_surface()
295 r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, in r600_init_surface()
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Dradeon_vce.c222 struct si_screen *sscreen = (struct si_screen *)enc->screen; in si_vce_frame_offset() local
225 if (sscreen->info.chip_class < GFX9) { in si_vce_frame_offset()
391 struct si_screen *sscreen = (struct si_screen *)context->screen; in si_vce_create_encoder() local
398 if (!sscreen->info.vce_fw_version) { in si_vce_create_encoder()
402 } else if (!si_vce_is_fw_version_supported(sscreen)) { in si_vce_create_encoder()
411 if (sscreen->info.drm_major == 3) in si_vce_create_encoder()
413 if ((sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42) || in si_vce_create_encoder()
414 sscreen->info.drm_major == 3) in si_vce_create_encoder()
416 if (sscreen->info.family >= CHIP_TONGA && in si_vce_create_encoder()
417 sscreen->info.family != CHIP_STONEY && in si_vce_create_encoder()
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Dr600_pipe_common.c406 struct si_screen *sscreen, in si_common_context_init() argument
409 slab_create_child(&rctx->pool_transfers, &sscreen->pool_transfers); in si_common_context_init()
410 slab_create_child(&rctx->pool_transfers_unsync, &sscreen->pool_transfers); in si_common_context_init()
412 rctx->screen = sscreen; in si_common_context_init()
413 rctx->ws = sscreen->ws; in si_common_context_init()
414 rctx->family = sscreen->info.family; in si_common_context_init()
415 rctx->chip_class = sscreen->info.chip_class; in si_common_context_init()
419 if (sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 43) { in si_common_context_init()
435 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, in si_common_context_init()
436 16 * sscreen->info.num_render_backends); in si_common_context_init()
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Dr600_buffer_common.c102 void si_init_resource_fields(struct si_screen *sscreen, in si_init_resource_fields() argument
127 if (sscreen->info.drm_major == 2 && in si_init_resource_fields()
128 sscreen->info.drm_minor < 40) { in si_init_resource_fields()
155 if (sscreen->info.drm_major == 2 && in si_init_resource_fields()
156 sscreen->info.drm_minor < 40) in si_init_resource_fields()
174 if (sscreen->debug_flags & DBG(NO_WC)) in si_init_resource_fields()
191 sscreen->info.has_dedicated_vram && in si_init_resource_fields()
192 size >= sscreen->info.vram_vis_size / 4 ? 1 : 0; in si_init_resource_fields()
198 bool si_alloc_resource(struct si_screen *sscreen, in si_alloc_resource() argument
204 new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size, in si_alloc_resource()
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Dr600_pipe_common.h534 void si_init_resource_fields(struct si_screen *sscreen,
537 bool si_alloc_resource(struct si_screen *sscreen,
547 void si_init_screen_buffer_functions(struct si_screen *sscreen);
560 struct si_screen *sscreen,
563 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
573 void si_gpu_load_kill_thread(struct si_screen *sscreen);
574 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
575 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
579 void si_perfcounters_destroy(struct si_screen *sscreen);
582 void si_init_screen_query_functions(struct si_screen *sscreen);
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Dr600_query.c58 static void r600_query_sw_destroy(struct si_screen *sscreen, in r600_query_sw_destroy() argument
63 sscreen->b.fence_reference(&sscreen->b, &query->fence, NULL); in r600_query_sw_destroy()
502 void si_query_hw_destroy(struct si_screen *sscreen, in si_query_hw_destroy() argument
521 static struct r600_resource *r600_new_query_buffer(struct si_screen *sscreen, in r600_new_query_buffer() argument
525 sscreen->info.min_alloc_size); in r600_new_query_buffer()
532 pipe_buffer_create(&sscreen->b, 0, in r600_new_query_buffer()
537 if (!query->ops->prepare_buffer(sscreen, query, buf)) { in r600_new_query_buffer()
545 static bool r600_query_hw_prepare_buffer(struct si_screen *sscreen, in r600_query_hw_prepare_buffer() argument
550 uint32_t *results = sscreen->ws->buffer_map(buffer->buf, NULL, in r600_query_hw_prepare_buffer()
561 unsigned max_rbs = sscreen->info.num_render_backends; in r600_query_hw_prepare_buffer()
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Dr600_perfcounter.c98 static void r600_pc_query_destroy(struct si_screen *sscreen, in r600_pc_query_destroy() argument
111 si_query_hw_destroy(sscreen, rquery); in r600_pc_query_destroy()
195 static void r600_pc_query_add_result(struct si_screen *sscreen, in r600_pc_query_add_result() argument
579 void si_perfcounters_destroy(struct si_screen *sscreen) in si_perfcounters_destroy() argument
581 if (sscreen->perfcounters) in si_perfcounters_destroy()
582 sscreen->perfcounters->cleanup(sscreen); in si_perfcounters_destroy()
598 void si_perfcounters_add_block(struct si_screen *sscreen, in si_perfcounters_add_block() argument
627 block->num_groups *= sscreen->info.max_se; in si_perfcounters_add_block()
Dr600_query.h200 bool si_query_hw_init(struct si_screen *sscreen,
202 void si_query_hw_destroy(struct si_screen *sscreen,
Dradeon_video.c83 struct si_screen *sscreen = (struct si_screen *)screen; in si_vid_resize_buffer() local
84 struct radeon_winsys* ws = sscreen->ws; in si_vid_resize_buffer()

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