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Searched refs:sshll2 (Results 1 – 25 of 42) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-shift-left-long.s11 sshll2 v0.8h, v1.16b, #3
12 sshll2 v0.4s, v1.8h, #3
13 sshll2 v0.2d, v1.4s, #3
Darm64-advsimd.s1546 sshll2.8h v0, v0, #2
1548 sshll2.4s v0, v0, #4
1550 sshll2.2d v0, v0, #6
1718 ; CHECK: sshll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x4f]
1720 ; CHECK: sshll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x4f]
1722 ; CHECK: sshll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x4f]
1854 sshll2 v10.8h, v3.16b, #6
1855 sshll2 v11.4s, v4.8h, #5
1856 sshll2 v12.2d, v5.4s, #4
1917 ; CHECK: sshll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x4f]
[all …]
Dneon-diagnostics.s1333 sshll2 v0.2d, v3.8s, #15
1341 sshll2 v0.8h, v1.16b, #9
1342 sshll2 v0.4s, v1.8h, #17
/external/llvm/test/MC/AArch64/
Dneon-shift-left-long.s11 sshll2 v0.8h, v1.16b, #3
12 sshll2 v0.4s, v1.8h, #3
13 sshll2 v0.2d, v1.4s, #3
Darm64-advsimd.s1546 sshll2.8h v0, v0, #2
1548 sshll2.4s v0, v0, #4
1550 sshll2.2d v0, v0, #6
1718 ; CHECK: sshll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x4f]
1720 ; CHECK: sshll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x4f]
1722 ; CHECK: sshll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x4f]
1854 sshll2 v10.8h, v3.16b, #6
1855 sshll2 v11.4s, v4.8h, #5
1856 sshll2 v12.2d, v5.4s, #4
1917 ; CHECK: sshll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x4f]
[all …]
Dneon-diagnostics.s1328 sshll2 v0.2d, v3.8s, #15
1336 sshll2 v0.8h, v1.16b, #9
1337 sshll2 v0.4s, v1.8h, #17
/external/capstone/suite/MC/AArch64/
Dneon-shift-left-long.s.cs5 0x20,0xa4,0x0b,0x4f = sshll2 v0.8h, v1.16b, #3
6 0x20,0xa4,0x13,0x4f = sshll2 v0.4s, v1.8h, #3
7 0x20,0xa4,0x23,0x4f = sshll2 v0.2d, v1.4s, #3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dsitofp-fixed-legal.ll7 ; CHECK-DAG: sshll2.2d [[BLOCK0_HI:v[0-9]+]], v0, #0
8 ; CHECK-DAG: sshll2.2d [[BLOCK1_HI:v[0-9]+]], v1, #0
9 ; CHECK-DAG: sshll2.2d [[BLOCK2_HI:v[0-9]+]], v2, #0
10 ; CHECK-DAG: sshll2.2d [[BLOCK3_HI:v[0-9]+]], v3, #0
Darm64-subvector-extend.ll36 ; CHECK-NEXT: sshll2.8h v1, v0, #0
74 ; CHECK-NEXT: sshll2.4s v1, v0, #0
94 ; CHECK-NEXT: sshll2.4s v1, v0, #0
116 ; CHECK-NEXT: sshll2.2d v1, v0, #0
136 ; CHECK-NEXT: sshll2.2d v1, v0, #0
Dneon-shift-left-long.ll53 ; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
62 ; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
71 ; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
149 ; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
157 ; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
165 ; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
Dfp16-v8-instructions.ll284 ; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
298 ; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
/external/llvm/test/CodeGen/AArch64/
Darm64-subvector-extend.ll36 ; CHECK-NEXT: sshll2.8h v1, v0, #0
74 ; CHECK-NEXT: sshll2.4s v1, v0, #0
94 ; CHECK-NEXT: sshll2.4s v1, v0, #0
116 ; CHECK-NEXT: sshll2.2d v1, v0, #0
136 ; CHECK-NEXT: sshll2.2d v1, v0, #0
Dneon-shift-left-long.ll53 ; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
62 ; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
71 ; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
149 ; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
157 ; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
165 ; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
Dfp16-v8-instructions.ll260 ; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
274 ; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
Darm64-vshift.ll1224 ;CHECK: sshll2.8h v0, {{v[0-9]+}}, #1
1234 ;CHECK: sshll2.4s v0, {{v[0-9]+}}, #1
1244 ;CHECK: sshll2.2d v0, {{v[0-9]+}}, #1
/external/libjpeg-turbo/simd/arm64/
Djsimd_neon.S494 … sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
499 … sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
754 … sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
757 … sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
833 … sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
838 … sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2121 # CHECK: sshll2.8h v0, v0, #0x2
2123 # CHECK: sshll2.4s v0, v0, #0x4
2125 # CHECK: sshll2.2d v0, v0, #0x6
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2121 # CHECK: sshll2.8h v0, v0, #0x2
2123 # CHECK: sshll2.4s v0, v0, #0x4
2125 # CHECK: sshll2.2d v0, v0, #0x6
/external/v8/src/arm64/
Dmacro-assembler-arm64.h1065 V(sshll2, Sshll2) \
Dsimulator-logic-arm64.cc1357 LogicVRegister Simulator::sshll2(VectorFormat vform, LogicVRegister dst, in sshll2() function in v8::internal::Simulator
1375 return sshll2(vform, dst, src, shift); in shll2()
Dsimulator-arm64.h1736 LogicVRegister sshll2(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.cc2050 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) { in sshll2() function in v8::internal::Assembler
2060 sshll2(vd, vn, 0); in sxtl2()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1529 0x~~~~~~~~~~~~~~~~ 4f2ea48a sshll2 v10.2d, v4.4s, #14
1530 0x~~~~~~~~~~~~~~~~ 4f16a7fa sshll2 v26.4s, v31.8h, #6
1531 0x~~~~~~~~~~~~~~~~ 4f0ca743 sshll2 v3.8h, v26.16b, #4
Dlog-disasm1529 0x~~~~~~~~~~~~~~~~ 4f2ea48a sshll2 v10.2d, v4.4s, #14
1530 0x~~~~~~~~~~~~~~~~ 4f16a7fa sshll2 v26.4s, v31.8h, #6
1531 0x~~~~~~~~~~~~~~~~ 4f0ca743 sshll2 v3.8h, v26.16b, #4
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1762 __ sshll2(v10.V2D(), v4.V4S(), 14); in GenerateTestSequenceNEON() local
1763 __ sshll2(v26.V4S(), v31.V8H(), 6); in GenerateTestSequenceNEON() local
1764 __ sshll2(v3.V8H(), v26.V16B(), 4); in GenerateTestSequenceNEON() local

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