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Searched refs:ssubl2 (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s57 ssubl2 v0.8h, v1.16b, v2.16b
58 ssubl2 v0.4s, v1.8h, v2.8h
59 ssubl2 v0.2d, v1.4s, v2.4s
Dneon-diagnostics.s2169 ssubl2 v0.8h, v1.16h, v2.16b
2170 ssubl2 v0.4s, v1.8s, v2.8h
2171 ssubl2 v0.2d, v1.4d, v2.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-3vdiff.s57 ssubl2 v0.8h, v1.16b, v2.16b
58 ssubl2 v0.4s, v1.8h, v2.8h
59 ssubl2 v0.2d, v1.4s, v2.4s
Dneon-diagnostics.s2170 ssubl2 v0.8h, v1.16h, v2.16b
2171 ssubl2 v0.4s, v1.8s, v2.8h
2172 ssubl2 v0.2d, v1.4d, v2.4s
/external/capstone/suite/MC/AArch64/
Dneon-3vdiff.s.cs17 0x20,0x20,0x22,0x4e = ssubl2 v0.8h, v1.16b, v2.16b
18 0x20,0x20,0x62,0x4e = ssubl2 v0.4s, v1.8h, v2.8h
19 0x20,0x20,0xa2,0x4e = ssubl2 v0.2d, v1.4s, v2.4s
/external/llvm/test/CodeGen/AArch64/
Darm64-vsub.ll160 ;CHECK: ssubl2.8h
175 ;CHECK: ssubl2.4s
190 ;CHECK: ssubl2.2d
Darm64-neon-3vdiff.ll361 ; CHECK: ssubl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
373 ; CHECK: ssubl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
385 ; CHECK: ssubl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
Darm64-vadd.ll792 ; CHECK: ssubl2.2d
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s662 ssubl2 v23.4s, v13.8h, v11.8h
668 ssubl2 v27.4s, v15.8h, v9.8h
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AArch64/
Dfree-widening-casts.ll269 ; CODE: ssubl2 v2.8h, v0.16b, v1.16b
282 ; CODE: ssubl2 v2.4s, v0.8h, v1.8h
295 ; CODE: ssubl2 v2.2d, v0.4s, v1.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1160 # CHECK: ssubl2 v0.8h, v1.16b, v2.16b
1161 # CHECK: ssubl2 v0.4s, v1.8h, v2.8h
1162 # CHECK: ssubl2 v0.2d, v1.4s, v2.4s
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1160 # CHECK: ssubl2 v0.8h, v1.16b, v2.16b
1161 # CHECK: ssubl2 v0.4s, v1.8h, v2.8h
1162 # CHECK: ssubl2 v0.2d, v1.4s, v2.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-3vdiff.ll361 ; CHECK: ssubl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
373 ; CHECK: ssubl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
385 ; CHECK: ssubl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
Darm64-vadd.ll792 ; CHECK: ssubl2.2d
/external/v8/src/arm64/
Dmacro-assembler-arm64.h464 V(ssubl2, Ssubl2) \
Dsimulator-arm64.h1688 LogicVRegister ssubl2(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.h2091 void ssubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1551 0x~~~~~~~~~~~~~~~~ 4eb921a5 ssubl2 v5.2d, v13.4s, v25.4s
1552 0x~~~~~~~~~~~~~~~~ 4e7121e3 ssubl2 v3.4s, v15.8h, v17.8h
1553 0x~~~~~~~~~~~~~~~~ 4e2e21ef ssubl2 v15.8h, v15.16b, v14.16b
Dlog-disasm1551 0x~~~~~~~~~~~~~~~~ 4eb921a5 ssubl2 v5.2d, v13.4s, v25.4s
1552 0x~~~~~~~~~~~~~~~~ 4e7121e3 ssubl2 v3.4s, v15.8h, v17.8h
1553 0x~~~~~~~~~~~~~~~~ 4e2e21ef ssubl2 v15.8h, v15.16b, v14.16b
Dlog-cpufeatures-custom1550 0x~~~~~~~~~~~~~~~~ 4eb921a5 ssubl2 v5.2d, v13.4s, v25.4s ### {NEON} ###
1551 0x~~~~~~~~~~~~~~~~ 4e7121e3 ssubl2 v3.4s, v15.8h, v17.8h ### {NEON} ###
1552 0x~~~~~~~~~~~~~~~~ 4e2e21ef ssubl2 v15.8h, v15.16b, v14.16b ### {NEON} ###
Dlog-cpufeatures1550 0x~~~~~~~~~~~~~~~~ 4eb921a5 ssubl2 v5.2d, v13.4s, v25.4s // Needs: NEON
1551 0x~~~~~~~~~~~~~~~~ 4e7121e3 ssubl2 v3.4s, v15.8h, v17.8h // Needs: NEON
1552 0x~~~~~~~~~~~~~~~~ 4e2e21ef ssubl2 v15.8h, v15.16b, v14.16b // Needs: NEON
Dlog-cpufeatures-colour1550 0x~~~~~~~~~~~~~~~~ 4eb921a5 ssubl2 v5.2d, v13.4s, v25.4s NEON
1551 0x~~~~~~~~~~~~~~~~ 4e7121e3 ssubl2 v3.4s, v15.8h, v17.8h NEON
1552 0x~~~~~~~~~~~~~~~~ 4e2e21ef ssubl2 v15.8h, v15.16b, v14.16b NEON
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1784 __ ssubl2(v5.V2D(), v13.V4S(), v25.V4S()); in GenerateTestSequenceNEON() local
1785 __ ssubl2(v3.V4S(), v15.V8H(), v17.V8H()); in GenerateTestSequenceNEON() local
1786 __ ssubl2(v15.V8H(), v15.V16B(), v14.V16B()); in GenerateTestSequenceNEON() local
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2450 LogicVRegister ssubl2(VectorFormat vform,
Dassembler-aarch64.h3087 void ssubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);

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