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Searched refs:ssubw (Results 1 – 25 of 40) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s333 ssubw v0.8h, v1.8h, v2.8b
334 ssubw v0.4s, v1.4s, v2.4h
335 ssubw v0.2d, v1.2d, v2.2s
Dneon-diagnostics.s2703 ssubw v0.8h, v1.8h, v2.8h
2704 ssubw v0.4s, v1.4s, v2.4s
2705 ssubw v0.2d, v1.2d, v2.2d
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-3vdiff.s333 ssubw v0.8h, v1.8h, v2.8b
334 ssubw v0.4s, v1.4s, v2.4h
335 ssubw v0.2d, v1.2d, v2.2s
Dneon-diagnostics.s2652 ssubw v0.8h, v1.8h, v2.8h
2653 ssubw v0.4s, v1.4s, v2.4s
2654 ssubw v0.2d, v1.2d, v2.2d
/external/capstone/suite/MC/AArch64/
Dneon-3vdiff.s.cs114 0x20,0x30,0x22,0x0e = ssubw v0.8h, v1.8h, v2.8b
115 0x20,0x30,0x62,0x0e = ssubw v0.4s, v1.4s, v2.4h
116 0x20,0x30,0xa2,0x0e = ssubw v0.2d, v1.2d, v2.2s
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vsub.ll283 ;CHECK: ssubw.8h
293 ;CHECK: ssubw.4s
303 ;CHECK: ssubw.2d
313 ;CHECK: ssubw.8h
326 ;CHECK: ssubw.4s
339 ;CHECK: ssubw.2d
Darm64-neon-3vdiff.ll433 ; CHECK: ssubw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
442 ; CHECK: ssubw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
451 ; CHECK: ssubw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s674 ssubw v22.4s, v22.4s, v15.4h
683 ssubw v28.4s, v28.4s, v11.4h
687 ssubw v22.4s, v22.4s, v21.4h
696 ssubw v28.4s, v28.4s, v18.4h
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AArch64/
Dfree-widening-casts.ll496 ; CODE: ssubw v0.8h, v1.8h, v0.8b
506 ; CODE: ssubw v0.4s, v1.4s, v0.4h
516 ; CODE: ssubw v0.2d, v1.2d, v0.2s
527 ; CODE-NEXT: ssubw v0.8h, v1.8h, v0.8b
538 ; CODE-NEXT: ssubw v0.4s, v1.4s, v0.4h
549 ; CODE-NEXT: ssubw v0.2d, v1.2d, v0.2s
/external/libhevc/common/arm64/
Dihevc_deblk_luma_horz.s509 ssubw v4.8h, v6.8h , v7.8b
563 ssubw v14.8h, v14.8h , v7.8b
Dihevc_deblk_luma_vert.s588 ssubw v2.8h, v2.8h , v20.8b
/external/llvm/test/CodeGen/AArch64/
Darm64-vsub.ll283 ;CHECK: ssubw.8h
293 ;CHECK: ssubw.4s
303 ;CHECK: ssubw.2d
Darm64-neon-3vdiff.ll433 ; CHECK: ssubw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
442 ; CHECK: ssubw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
451 ; CHECK: ssubw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1398 # CHECK: ssubw v0.8h, v1.8h, v2.8b
1399 # CHECK: ssubw v0.4s, v1.4s, v2.4h
1400 # CHECK: ssubw v0.2d, v1.2d, v2.2s
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1398 # CHECK: ssubw v0.8h, v1.8h, v2.8b
1399 # CHECK: ssubw v0.4s, v1.4s, v2.4h
1400 # CHECK: ssubw v0.2d, v1.2d, v2.2s
/external/v8/src/arm64/
Dmacro-assembler-arm64.h467 V(ssubw, Ssubw) \
Dsimulator-arm64.h1690 LogicVRegister ssubw(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.h2094 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1554 0x~~~~~~~~~~~~~~~~ 0eba32f9 ssubw v25.2d, v23.2d, v26.2s
1555 0x~~~~~~~~~~~~~~~~ 0e783255 ssubw v21.4s, v18.4s, v24.4h
1556 0x~~~~~~~~~~~~~~~~ 0e2332de ssubw v30.8h, v22.8h, v3.8b
Dlog-disasm1554 0x~~~~~~~~~~~~~~~~ 0eba32f9 ssubw v25.2d, v23.2d, v26.2s
1555 0x~~~~~~~~~~~~~~~~ 0e783255 ssubw v21.4s, v18.4s, v24.4h
1556 0x~~~~~~~~~~~~~~~~ 0e2332de ssubw v30.8h, v22.8h, v3.8b
Dlog-cpufeatures-custom1553 0x~~~~~~~~~~~~~~~~ 0eba32f9 ssubw v25.2d, v23.2d, v26.2s ### {NEON} ###
1554 0x~~~~~~~~~~~~~~~~ 0e783255 ssubw v21.4s, v18.4s, v24.4h ### {NEON} ###
1555 0x~~~~~~~~~~~~~~~~ 0e2332de ssubw v30.8h, v22.8h, v3.8b ### {NEON} ###
Dlog-cpufeatures1553 0x~~~~~~~~~~~~~~~~ 0eba32f9 ssubw v25.2d, v23.2d, v26.2s // Needs: NEON
1554 0x~~~~~~~~~~~~~~~~ 0e783255 ssubw v21.4s, v18.4s, v24.4h // Needs: NEON
1555 0x~~~~~~~~~~~~~~~~ 0e2332de ssubw v30.8h, v22.8h, v3.8b // Needs: NEON
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1787 __ ssubw(v25.V2D(), v23.V2D(), v26.V2S()); in GenerateTestSequenceNEON() local
1788 __ ssubw(v21.V4S(), v18.V4S(), v24.V4H()); in GenerateTestSequenceNEON() local
1789 __ ssubw(v30.V8H(), v22.V8H(), v3.V8B()); in GenerateTestSequenceNEON() local
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2454 LogicVRegister ssubw(VectorFormat vform,
Dassembler-aarch64.h3090 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);

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