| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 18 stllr w0,[x1]
19 stllr x0,[x1]
40 stllr w0,[w1]
|
| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 18 stllr w0,[x1]
19 stllr x0,[x1]
40 stllr w0,[w1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 17 # CHECK: stllr w0, [x1]
18 # CHECK: stllr x0, [x1]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 17 # CHECK: stllr w0, [x1]
18 # CHECK: stllr x0, [x1]
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1956 COMPARE(stllr(w19, MemOperand(x20)), "stllr w19, [x20]"); in TEST()
1957 COMPARE(stllr(w21, MemOperand(sp)), "stllr w21, [sp]"); in TEST()
1958 COMPARE(stllr(x22, MemOperand(x23)), "stllr x22, [x23]"); in TEST()
1959 COMPARE(stllr(x24, MemOperand(sp)), "stllr x24, [sp]"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 3458 TEST_LOREGIONS(stllr_0, stllr(w0, MemOperand(x1, 0)))
3459 TEST_LOREGIONS(stllr_1, stllr(x0, MemOperand(x1, 0)))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1397 void stllr(const Register& rt, const MemOperand& dst);
|
| D | macro-assembler-aarch64.h | 2238 stllr(rt, dst); in Stllr()
|
| D | assembler-aarch64.cc | 1541 void Assembler::stllr(const Register& rt, const MemOperand& dst) { in stllr() function in vixl::aarch64::Assembler
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2483 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2484 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2764 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2765 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 11916 "rb\006steorh\006steorl\007steorlb\007steorlh\005stllr\006stllrb\006stll"
17376 …{ 4668 /* stllr */, AArch64::STLLRW, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32, …
17377 …{ 4668 /* stllr */, AArch64::STLLRX, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR64, …
23845 …{ 4668 /* stllr */, AArch64::STLLRW, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32, …
23846 …{ 4668 /* stllr */, AArch64::STLLRX, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR64, …
34101 { Feature_HasV8_1a, 4668 /* stllr */, MCK_GPR64sp0, 4 /* 2 */ },
34102 { Feature_HasV8_1a, 4668 /* stllr */, MCK_GPR64sp0, 4 /* 2 */ },
34103 { Feature_HasV8_1a, 4668 /* stllr */, MCK_GPR64sp0, 4 /* 2 */ },
34104 { Feature_HasV8_1a, 4668 /* stllr */, MCK_GPR64sp0, 4 /* 2 */ },
|