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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll236 %res = call i32 @llvm.aarch64.stlxr.p0i8(i64 %extval, i8* %addr)
246 %res = call i32 @llvm.aarch64.stlxr.p0i16(i64 %extval, i16* %addr)
254 ; CHECK: stlxr w0, w1, [x2]
256 %res = call i32 @llvm.aarch64.stlxr.p0i32(i64 %extval, i32* %addr)
262 ; CHECK: stlxr w0, x1, [x2]
263 %res = call i32 @llvm.aarch64.stlxr.p0i64(i64 %val, i64* %addr)
267 declare i32 @llvm.aarch64.stlxr.p0i8(i64, i8*) nounwind
268 declare i32 @llvm.aarch64.stlxr.p0i16(i64, i16*) nounwind
269 declare i32 @llvm.aarch64.stlxr.p0i32(i64, i32*) nounwind
270 declare i32 @llvm.aarch64.stlxr.p0i64(i64, i64*) nounwind
Dfast-isel-cmpxchg.ll10 ; CHECK-NEXT: stlxr [[STATUS]], w2, [x0]
36 ; CHECK-NEXT: stlxr [[STATUS]], [[NEW]], [x0]
61 ; CHECK-NEXT: stlxr [[STATUS]], x2, [x0]
Dcmpxchg-idioms.ll11 ; CHECK: stlxr [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
65 ; CHECK: stlxr [[STATUS:w[0-9]+]], w2, [x0]
101 ; CHECK: stlxr [[STATUS:w[0-9]+]], w20, [x19]
Darm64-atomic.ll49 ; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
84 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
85 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
99 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
112 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
113 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
Datomic-ops.ll67 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
167 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
227 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
327 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
387 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
465 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w8, [x[[ADDR]]]
580 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
654 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
750 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
774 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
[all …]
Dcmpxchg-O0.ll42 ; CHECK: stlxr [[STATUS]], w2, [x0]
58 ; CHECK: stlxr [[STATUS]], x2, [x0]
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll236 %res = call i32 @llvm.aarch64.stlxr.p0i8(i64 %extval, i8* %addr)
246 %res = call i32 @llvm.aarch64.stlxr.p0i16(i64 %extval, i16* %addr)
254 ; CHECK: stlxr w0, w1, [x2]
256 %res = call i32 @llvm.aarch64.stlxr.p0i32(i64 %extval, i32* %addr)
262 ; CHECK: stlxr w0, x1, [x2]
263 %res = call i32 @llvm.aarch64.stlxr.p0i64(i64 %val, i64* %addr)
267 declare i32 @llvm.aarch64.stlxr.p0i8(i64, i8*) nounwind
268 declare i32 @llvm.aarch64.stlxr.p0i16(i64, i16*) nounwind
269 declare i32 @llvm.aarch64.stlxr.p0i32(i64, i32*) nounwind
270 declare i32 @llvm.aarch64.stlxr.p0i64(i64, i64*) nounwind
Dcmpxchg-idioms.ll11 ; CHECK: stlxr [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
66 ; CHECK: stlxr [[STATUS:w[0-9]+]], w2, [x0]
Darm64-atomic.ll47 ; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]
82 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
83 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
97 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
110 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
111 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
Dcmpxchg-O0.ll39 ; CHECK: stlxr [[STATUS:w[3-9]]], w2, [x0]
54 ; CHECK: stlxr [[STATUS:w[3-9]]], x2, [x0]
Datomic-ops.ll67 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
167 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
227 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
327 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
387 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
464 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
581 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
655 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
751 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
775 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-memory.s524 stlxr w8, x7, [x1]
525 stlxr w8, w7, [x1]
531 ; CHECK: stlxr w8, x7, [x1] ; encoding: [0x27,0xfc,0x08,0xc8]
532 ; CHECK: stlxr w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x88]
Darm64-diags.s256 stlxr w22, x1, [x22]
258 stlxr w5, x0, [x5]
275 ; CHECK-ERRORS: stlxr w22, x1, [x22]
281 ; CHECK-ERRORS: stlxr w5, x0, [x5]
Dbasic-a64-diagnostics.s1892 stlxr x20, w21, [sp]
Dbasic-a64-instructions.s2270 stlxr wzr, w17, [sp]
2271 stlxr w18, x19, [x20]
/external/llvm/test/MC/AArch64/
Darm64-memory.s524 stlxr w8, x7, [x1]
525 stlxr w8, w7, [x1]
531 ; CHECK: stlxr w8, x7, [x1] ; encoding: [0x27,0xfc,0x08,0xc8]
532 ; CHECK: stlxr w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x88]
Dbasic-a64-diagnostics.s1869 stlxr x20, w21, [sp]
Dbasic-a64-instructions.s2287 stlxr wzr, w17, [sp]
2288 stlxr w18, x19, [x20]
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc1630 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxr, stlxr, Register32); in AssembleArchInstruction()
1633 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxr, stlxr, Register); in AssembleArchInstruction()
1657 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxr, stlxr, UXTW, Register32); in AssembleArchInstruction()
1660 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxr, stlxr, UXTX, Register); in AssembleArchInstruction()
1681 ASSEMBLE_ATOMIC_BINOP(ldaxr, stlxr, inst, Register32); \ in AssembleArchInstruction()
1684 ASSEMBLE_ATOMIC_BINOP(ldaxr, stlxr, inst, Register); \ in AssembleArchInstruction()
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-memory.txt512 # CHECK: stlxr w8, x7, [x1]
513 # CHECK: stlxr w8, w7, [x1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-memory.txt512 # CHECK: stlxr w8, x7, [x1]
513 # CHECK: stlxr w8, w7, [x1]
/external/vixl/
DREADME.md125 `stlxrh`, `stlxr`, `ldaxrb`, `ldaxrh`, `ldaxr`, `stlxp`, `ldaxp`, `stlrb`,
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs890 0xf1,0xff,0x1f,0x88 = stlxr wzr, w17, [sp]
891 0x93,0xfe,0x12,0xc8 = stlxr w18, x19, [x20]
/external/v8/src/arm64/
Dmacro-assembler-arm64.h99 V(Stlxr, stlxr)
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc1912 COMPARE(stlxr(w30, w0, MemOperand(x1)), "stlxr w30, w0, [x1]"); in TEST()
1913 COMPARE(stlxr(x2, w3, MemOperand(sp)), "stlxr w2, w3, [sp]"); in TEST()
1914 COMPARE(stlxr(w4, x5, MemOperand(x6)), "stlxr w4, x5, [x6]"); in TEST()
1915 COMPARE(stlxr(x7, x8, MemOperand(sp)), "stlxr w7, x8, [sp]"); in TEST()

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