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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll99 %res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr)
109 %res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr)
117 ; CHECK: stxr w0, w1, [x2]
119 %res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr)
125 ; CHECK: stxr w0, x1, [x2]
126 %res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr)
130 declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) nounwind
131 declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) nounwind
132 declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*) nounwind
133 declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) nounwind
Darm64-atomic.ll10 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
28 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0]
67 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
126 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
Datomic-ops.ll87 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
147 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
247 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
307 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
407 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
482 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
556 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
678 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
967 ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll99 %res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr)
109 %res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr)
117 ; CHECK: stxr w0, w1, [x2]
119 %res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr)
125 ; CHECK: stxr w0, x1, [x2]
126 %res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr)
130 declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) nounwind
131 declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) nounwind
132 declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*) nounwind
133 declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) nounwind
Darm64-atomic.ll10 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
28 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0]
65 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
124 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
Datomic-ops.ll87 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
147 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
247 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
307 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
407 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
483 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
557 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
679 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
968 ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-canonical-form.txt5 # CHECK: stxr w0, x0, [x0]
Darm64-memory.txt456 # CHECK: stxr w1, x4, [x3]
457 # CHECK: stxr w1, w4, [x3]
Dbasic-a64-instructions.txt1904 #CHECK: stxr w5, w6, [x17]
1905 #CHECK: stxr w1, x10, [x21]
1906 #CHECK: stxr w1, x10, [x21]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-canonical-form.txt5 # CHECK: stxr w0, x0, [x0]
Darm64-memory.txt456 # CHECK: stxr w1, x4, [x3]
457 # CHECK: stxr w1, w4, [x3]
Dbasic-a64-instructions.txt1920 #CHECK: stxr w5, w6, [x17]
1921 #CHECK: stxr w1, x10, [x21]
1922 #CHECK: stxr w1, x10, [x21]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-memory.s468 stxr w1, x4, [x3]
469 stxr w1, w4, [x3]
475 ; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8]
476 ; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
Darm64-diags.s255 stxr w9, w9, [x12]
257 stxr w4, x4, [x9]
272 ; CHECK-ERRORS: stxr w9, w9, [x12]
278 ; CHECK-ERRORS: stxr w4, x4, [x9]
Dbasic-a64-instructions.s2242 stxr wzr, w4, [sp]
2243 stxr w5, x6, [x7]
/external/llvm/test/MC/AArch64/
Darm64-memory.s468 stxr w1, x4, [x3]
469 stxr w1, w4, [x3]
475 ; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8]
476 ; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
Dbasic-a64-instructions.s2259 stxr wzr, w4, [sp]
2260 stxr w5, x6, [x7]
/external/vixl/
DREADME.md124 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs878 0xe4,0x7f,0x1f,0x88 = stxr wzr, w4, [sp]
879 0xe6,0x7c,0x05,0xc8 = stxr w5, x6, [x7]
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc1880 COMPARE(stxr(w20, w21, MemOperand(x22)), "stxr w20, w21, [x22]"); in TEST()
1881 COMPARE(stxr(x23, w24, MemOperand(sp)), "stxr w23, w24, [sp]"); in TEST()
1882 COMPARE(stxr(w25, x26, MemOperand(x27)), "stxr w25, x26, [x27]"); in TEST()
1883 COMPARE(stxr(x28, x29, MemOperand(sp)), "stxr w28, x29, [sp]"); in TEST()
Dtest-trace-aarch64.cc337 __ stxr(w12, w13, MemOperand(x0)); in GenerateTestSequenceBase() local
338 __ stxr(x14, x15, MemOperand(x0)); in GenerateTestSequenceBase() local
/external/vixl/src/aarch64/
Dassembler-aarch64.h1325 void stxr(const Register& rs, const Register& rt, const MemOperand& dst);
Dmacro-assembler-aarch64.h2305 stxr(rs, rt, dst); in Stxr()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour284 0x~~~~~~~~~~~~~~~~ 880c7c0d stxr w12, w13, [x0]
285 0x~~~~~~~~~~~~~~~~ c80e7c0f stxr w14, x15, [x0]
Dlog-disasm284 0x~~~~~~~~~~~~~~~~ 880c7c0d stxr w12, w13, [x0]
285 0x~~~~~~~~~~~~~~~~ c80e7c0f stxr w14, x15, [x0]

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