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Searched refs:sube (Results 1 – 25 of 44) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D2011-08-29-SchedCycle.ll3 ; When a i64 sub is expanded to subc + sube.
10 ; sube
22 ; sube
24 ; However since subc and sube are "glued" together, this ends up being a
25 ; cycle when the scheduler combine subc and sube as a single scheduling
30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
/external/llvm/test/CodeGen/ARM/
D2011-08-29-SchedCycle.ll3 ; When a i64 sub is expanded to subc + sube.
10 ; sube
22 ; sube
24 ; However since subc and sube are "glued" together, this ends up being a
25 ; cycle when the scheduler combine subc and sube as a single scheduling
30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2011-08-29-SchedCycle.ll3 ; When a i64 sub is expanded to subc + sube.
10 ; sube
22 ; sube
24 ; However since subc and sube are "glued" together, this ends up being a
25 ; cycle when the scheduler combine subc and sube as a single scheduling
30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
/external/libpng/scripts/
Doptions.awk52 sube=" \"@" # Substitute end
843 deflt = " " subs substr(deflt, 3) sube
864 print def i, subs "PNG_" i sube end >out
868 print def i, subs "PNG_set_" i sube end >out
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430InstrInfo.td870 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
875 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
881 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),
886 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),
892 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
897 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
904 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
909 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
915 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
920 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td878 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
883 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
889 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),
894 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),
900 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
905 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
912 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
917 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
923 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
928 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td870 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
875 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
881 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),
886 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),
892 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
897 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
904 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
909 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
915 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
920 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
[all …]
/external/apache-xml/src/main/java/org/apache/xml/serializer/
DHTMLEntities.properties250 sube=8838 key
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td367 defm SUBB_ : ALUarith<0b011, "subb", sube, i32lo16z, i32hi16>;
373 def : Pat<(sube GPR:$Rs1, i32lo16z:$imm),
379 def : Pat<(sube GPR:$Rs1, i32hi16:$imm),
393 defm SUBB_F_ : ALUarith<0b011, "subb.f", sube, i32lo16z, i32hi16>;
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td369 defm SUBB_ : ALUarith<0b011, "subb", sube, i32lo16z, i32hi16>;
375 def : Pat<(sube GPR:$Rs1, i32lo16z:$imm),
381 def : Pat<(sube GPR:$Rs1, i32hi16:$imm),
395 defm SUBB_F_ : ALUarith<0b011, "subb.f", sube, i32lo16z, i32hi16>;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstr64Bit.td373 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
376 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
379 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
DPPCInstrInfo.td1210 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1213 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1216 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td444 [(set i8:$rd, (sube i8:$src, i8:$rr)),
455 [(set i16:$rd, (sube i16:$src, i16:$rr)),
462 [(set i8:$rd, (sube i8:$src, imm:$k)),
471 [(set i16:$rd, (sube i16:$src, imm:$rr)),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td478 [(set i8:$rd, (sube i8:$src, i8:$rr)),
489 [(set i16:$rd, (sube i16:$src, i16:$rr)),
496 [(set i8:$rd, (sube i8:$src, imm:$k)),
505 [(set i16:$rd, (sube i16:$src, imm:$rr)),
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrInfo.td372 def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIC_ALU>;
426 def RSUBIC : ArithRI<0x0B, "rsubic ", sube, simm16, immSExt16>;
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td541 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
544 [(set i64:$rT, (sube -1, i64:$rA))]>;
547 [(set i64:$rT, (sube 0, i64:$rA))]>;
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td992 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
993 def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
996 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
997 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTarget.td210 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
214 // let SubRegIndices = [sube, subo] in {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td590 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
593 [(set i64:$rT, (sube -1, i64:$rA))]>;
596 [(set i64:$rT, (sube 0, i64:$rA))]>;
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrInfo.td791 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2)),
795 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2)),
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td330 def SubCCCV4I32 : VecBinaryOp<V4AsmStr<"subc.cc.s32">, sube, V4I32Regs,
332 def SubCCCV2I32 : VecBinaryOp<V2AsmStr<"subc.cc.s32">, sube, V2I32Regs,
/external/llvm/include/llvm/Target/
DTarget.td262 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
266 // let SubRegIndices = [sube, subo] in {
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcInstrInfo.td476 defm SUBX : F3_12 <"subx" , 0b001100, sube>;
/external/v8/src/ppc/
Dassembler-ppc.h1030 void sube(Register dst, Register src1, Register src2, OEBit s = LeaveOE,
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTarget.td335 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
339 // let SubRegIndices = [sube, subo] in {

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