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Searched refs:surface_count (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/intel/vulkan/
Danv_pipeline_cache.c49 bind_map->surface_count); in anv_shader_bin_create()
77 bind_map->surface_count); in anv_shader_bin_create()
113 ok = blob_write_uint32(blob, shader->bind_map.surface_count); in anv_shader_bin_write_to_blob()
117 shader->bind_map.surface_count * in anv_shader_bin_write_to_blob()
145 bind_map.surface_count = blob_read_uint32(blob); in anv_shader_bin_create_from_blob()
149 blob_read_bytes(blob, bind_map.surface_count * in anv_shader_bin_create_from_blob()
DgenX_pipeline.c876 uint32_t surface_count = 0; local
880 surface_count = map->surface_count;
884 GENX(BLEND_STATE_ENTRY_length) * surface_count;
894 for (unsigned i = 0; i < surface_count; i++) {
1096 return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
1348 for (int i = 0; i < bind_map->surface_count; i++) {
Danv_descriptor_set.c84 uint32_t surface_count[MESA_SHADER_STAGES] = { 0, }; in anv_CreateDescriptorSetLayout() local
144 set_layout->binding[b].stage[s].surface_index = surface_count[s]; in anv_CreateDescriptorSetLayout()
145 surface_count[s] += binding->descriptorCount; in anv_CreateDescriptorSetLayout()
DgenX_cmd_buffer.c1575 if (bias + map->surface_count == 0) { in emit_binding_table()
1581 bias + map->surface_count, in emit_binding_table()
1606 if (map->surface_count == 0) in emit_binding_table()
1619 for (uint32_t s = 0; s < map->surface_count; s++) { in emit_binding_table()
1982 assert(surface <= bind_map->surface_count); in cmd_buffer_flush_push_constants()
Danv_pipeline.c951 map.surface_count += num_rts; in anv_pipeline_compile_fs()
952 assert(map.surface_count <= 256); in anv_pipeline_compile_fs()
Danv_nir_apply_pipeline_layout.c368 map->surface_count += in anv_nir_apply_pipeline_layout()
Danv_blorp.c66 .surface_count = 0, in upload_blorp_shader()
Danv_private.h2065 uint32_t surface_count; member