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Searched refs:swizzle_mode (Results 1 – 25 of 27) sorted by relevance

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/external/libxcam/xcore/
Ddrm_bo_buffer.cpp55 uint32_t tiling_mode, swizzle_mode; in map() local
57 drm_intel_bo_get_tiling (_bo, &tiling_mode, &swizzle_mode); in map()
78 uint32_t tiling_mode, swizzle_mode; in unmap() local
80 drm_intel_bo_get_tiling (_bo, &tiling_mode, &swizzle_mode); in unmap()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_clear.c254 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
264 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
268 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
269 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
272 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
273 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
276 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
277 rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
Dsi_state.c2533 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) | in si_init_depth_surface()
2536 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode); in si_init_depth_surface()
3041 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) | in si_emit_framebuffer_state()
3042 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) | in si_emit_framebuffer_state()
3801 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode); in si_make_texture_descriptor()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_bufmgr.c387 bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in bo_alloc_internal()
550 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_name()
1096 bo->swizzle_mode = set_tiling.swizzle_mode; in bo_set_tiling_internal()
1103 uint32_t *swizzle_mode) in brw_bo_get_tiling() argument
1106 *swizzle_mode = bo->swizzle_mode; in brw_bo_get_tiling()
1167 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_prime_internal()
Dbrw_bufmgr.h139 uint32_t swizzle_mode; member
285 uint32_t *swizzle_mode);
Dintel_screen.c1809 uint32_t swizzle_mode = 0; in intel_detect_swizzling() local
1816 brw_bo_get_tiling(buffer, &tiling, &swizzle_mode); in intel_detect_swizzling()
1819 if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE) in intel_detect_swizzling()
/external/mesa3d/src/amd/common/
Dac_surface.c813 bool is_fmask, AddrSwizzleMode *swizzle_mode) in gfx9_get_preferred_swizzle_mode() argument
847 *swizzle_mode = sout.swizzleMode; in gfx9_get_preferred_swizzle_mode()
867 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
876 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
883 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3; in gfx9_compute_miptree()
1017 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode; in gfx9_compute_miptree()
1040 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode; in gfx9_compute_miptree()
1130 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode; in gfx9_compute_surface()
1180 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR; in gfx9_compute_surface()
1184 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode, in gfx9_compute_surface()
[all …]
Dac_surface.h114 uint16_t swizzle_mode; /* tile mode */ member
/external/libdrm/intel/
Dintel_bufmgr.c251 uint32_t * swizzle_mode) in drm_intel_bo_get_tiling() argument
254 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); in drm_intel_bo_get_tiling()
257 *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_bo_get_tiling()
Dintel_bufmgr_gem.c192 uint32_t swizzle_mode; member
294 uint32_t * swizzle_mode);
822 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_gem_bo_alloc_internal()
983 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_gem_bo_alloc_userptr()
1158 bo_gem->swizzle_mode = get_tiling.swizzle_mode; in drm_intel_bo_gem_create_from_name()
2574 bo_gem->swizzle_mode = set_tiling.swizzle_mode; in drm_intel_gem_bo_set_tiling_internal()
2609 uint32_t * swizzle_mode) in drm_intel_gem_bo_get_tiling() argument
2614 *swizzle_mode = bo_gem->swizzle_mode; in drm_intel_gem_bo_get_tiling()
2699 bo_gem->swizzle_mode = get_tiling.swizzle_mode; in drm_intel_bo_gem_create_from_prime()
Dintel_bufmgr_priv.h241 uint32_t * swizzle_mode);
Dintel_bufmgr.h163 uint32_t * swizzle_mode);
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_texture.c333 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode; in r600_texture_init_metadata()
357 if (metadata->u.gfx9.swizzle_mode > 0) in r600_surface_import_metadata()
362 *is_scanout = metadata->u.gfx9.swizzle_mode == 0 || in r600_surface_import_metadata()
363 metadata->u.gfx9.swizzle_mode % 4 == 2; in r600_surface_import_metadata()
365 surf->u.gfx9.surf.swizzle_mode = metadata->u.gfx9.swizzle_mode; in r600_surface_import_metadata()
1066 rtex->surface.u.gfx9.surf.swizzle_mode, in si_print_texture_info()
1076 rtex->surface.u.gfx9.fmask.swizzle_mode, in si_print_texture_info()
1112 rtex->surface.u.gfx9.stencil.swizzle_mode, in si_print_texture_info()
Dradeon_vcn_enc.h296 uint32_t swizzle_mode; member
Dradeon_winsys.h203 unsigned swizzle_mode:5; member
Dradeon_vcn_enc_1_2.c600 enc->enc_pic.ctx_buf.swizzle_mode = 0; in radeon_enc_ctx()
607 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); in radeon_enc_ctx()
/external/mesa3d/src/amd/vulkan/
Dradv_image.c288 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode); in si_set_mutable_tex_desc_fields()
291 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode); in si_set_mutable_tex_desc_fields()
557 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode); in si_make_texture_descriptor()
632 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode; in radv_init_metadata()
Dradv_radeon_winsys.h147 unsigned swizzle_mode:5; member
/external/mesa3d/include/drm-uapi/
Di915_drm.h1171 __u32 swizzle_mode; member
1188 __u32 swizzle_mode; member
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_screen.c1035 uint32_t swizzle_mode = 0; in intel_detect_swizzling() local
1043 drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode); in intel_detect_swizzling()
1046 if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE) in intel_detect_swizzling()
/external/libdrm/include/drm/
Di915_drm.h1213 __u32 swizzle_mode; member
1230 __u32 swizzle_mode; member
/external/kernel-headers/original/uapi/drm/
Di915_drm.h1243 __u32 swizzle_mode; member
1260 __u32 swizzle_mode; member
/external/mesa3d/src/intel/vulkan/
Danv_gem.c294 swizzled = get_tiling.swizzle_mode != I915_BIT_6_SWIZZLE_NONE; in anv_gem_get_bit6_swizzle()
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_bo.c508 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in radv_amdgpu_winsys_bo_set_metadata()
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_bo.c1093 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in amdgpu_buffer_get_metadata()
1126 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in amdgpu_buffer_set_metadata()

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