Home
last modified time | relevance | path

Searched refs:syscfg (Results 1 – 17 of 17) sorted by relevance

/external/u-boot/arch/arm/dts/
Dstih407-family.dtsi50 st,syscfg = <&syscfg_core 0x8e0>;
123 st,syscfg = <&syscfg_sbc_reg>;
142 syscfg_sbc: sbc-syscfg@9620000 {
143 compatible = "st,stih407-sbc-syscfg", "syscon";
147 syscfg_front: front-syscfg@9280000 {
148 compatible = "st,stih407-front-syscfg", "syscon";
152 syscfg_rear: rear-syscfg@9290000 {
153 compatible = "st,stih407-rear-syscfg", "syscon";
157 syscfg_flash: flash-syscfg@92a0000 {
158 compatible = "st,stih407-flash-syscfg", "syscon";
[all …]
Dstm32f469-disco-u-boot.dtsi38 st,syscfg = <&syscfg>;
86 &syscfg {
Dstm32429i-eval-u-boot.dtsi38 st,syscfg = <&syscfg>;
86 &syscfg {
Dstih410.dtsi19 st,syscfg = <&syscfg_core 0x8e0>;
20 st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
66 st,syscfg = <&syscfg_core 0xf8 0xf4>;
77 st,syscfg = <&syscfg_core 0xfc 0xf4>;
Dstm32f429-disco-u-boot.dtsi40 st,syscfg = <&syscfg>;
Dstm32f429.dtsi301 st,syscfg = <&pwrcfg>;
510 syscfg: system-config@40013800 { label
614 st,syscfg = <&pwrcfg>;
660 st,syscon = <&syscfg 0x4>;
Dstm32f4-pinctrl.dtsi54 st,syscfg = <&syscfg 0x8>;
Dstih407-pinctrl.dtsi52 st,syscfg = <&syscfg_sbc>;
376 st,syscfg = <&syscfg_front>;
939 st,syscfg = <&syscfg_front>;
972 st,syscfg = <&syscfg_rear>;
1202 st,syscfg = <&syscfg_flash>;
Dstm32h743.dtsi76 st,syscfg = <&pwrcfg>;
Dstm32f746.dtsi118 st,syscfg = <&pwrcfg>;
/external/u-boot/doc/device-tree-bindings/usb/
Ddwc3-st.txt9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
41 reg-names = "reg-glue", "syscfg-reg";
42 st,syscfg = <&syscfg_core>;
/external/u-boot/doc/device-tree-bindings/phy/
Dphy-stih407-usb.txt8 - st,syscfg : phandle of sysconfig bank plus integer array containing phyparam and phyctrl registe…
20 st,syscfg = <&syscfg_core 0x100 0xf4>;
/external/u-boot/doc/device-tree-bindings/clock/
Dst,stm32h7-rcc.txt25 - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
40 st,syscfg = <&pwrcfg>;
/external/u-boot/drivers/mtd/onenand/
Donenand_base.c2272 int syscfg, locked; in flexonenand_get_boundary() local
2275 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); in flexonenand_get_boundary()
2276 this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1); in flexonenand_get_boundary()
2300 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); in flexonenand_get_boundary()
2532 int syscfg; in onenand_chip_probe() local
2535 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); in onenand_chip_probe()
2538 this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ), in onenand_chip_probe()
2556 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); in onenand_chip_probe()
/external/u-boot/doc/device-tree-bindings/pinctrl/
Dst,stm32-pinctrl.txt37 - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
/external/u-boot/arch/arm/include/asm/arch-ep93xx/
Dep93xx.h619 uint32_t syscfg; member
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.td185 def SYSCFG : Ri<7, 2, "syscfg">;