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/external/python/cpython2/Modules/_ctypes/libffi/src/mips/
Dn32.S78 ADDU t4, v0, 2 * FFI_SIZEOF_ARG -1 # make sure it is aligned
79 and v0, t4, -2 * FFI_SIZEOF_ARG # to a proper boundry.
110 and t4, t6, ((1<<FFI_FLAG_BITS)-1)
112 beqz t4, arg1_next
113 bne t4, FFI_TYPE_FLOAT, arg1_doublep
120 SRL t4, t6, 1*FFI_FLAG_BITS
121 and t4, ((1<<FFI_FLAG_BITS)-1)
123 beqz t4, arg2_next
124 bne t4, FFI_TYPE_FLOAT, arg2_doublep
131 SRL t4, t6, 2*FFI_FLAG_BITS
[all …]
/external/libffi/src/mips/
Dn32.S78 ADDU t4, v0, 2 * FFI_SIZEOF_ARG -1 # make sure it is aligned
79 and v0, t4, -2 * FFI_SIZEOF_ARG # to a proper boundry.
110 and t4, t6, ((1<<FFI_FLAG_BITS)-1)
112 beqz t4, arg1_next
113 bne t4, FFI_TYPE_FLOAT, arg1_doublep
120 SRL t4, t6, 1*FFI_FLAG_BITS
121 and t4, ((1<<FFI_FLAG_BITS)-1)
123 beqz t4, arg2_next
124 bne t4, FFI_TYPE_FLOAT, arg2_doublep
131 SRL t4, t6, 2*FFI_FLAG_BITS
[all …]
/external/deqp-deps/glslang/Test/
Dspv.bufferhandle13.frag5 layout(set = 1, binding = 2, buffer_reference, std430) buffer t4 {
10 t4 m;
13 t4 f1(const t4 y) { return y; }
14 t4 f2(t4 y) { return y; }
15 t4 f3(const restrict t4 y) { return y; }
16 t4 f4(restrict t4 y) { return y; }
18 t4 g1;
19 restrict t4 g2;
23 t4 a = s5.m;
24 restrict t4 b = s5.m;
Dspv.bufferhandle3.frag9 layout(set = 1, binding = 2, buffer_reference, std430) buffer t4 {
15 t4 m;
18 flat in t4 k;
20 t4 foo(t4 y) { return y; }
/external/speex/libspeexdsp/
Dsmallft.c119 int t0,t1,t2,t3,t4,t5,t6; in dradf2() local
138 t4=(t1<<1)+(ido<<1); in dradf2()
143 t4-=2; in dradf2()
149 ch[t4]=ti2-cc[t5]; in dradf2()
151 ch[t4-1]=cc[t5-1]-tr2; in dradf2()
174 int i,k,t0,t1,t2,t3,t4,t5,t6; in dradf4() local
179 t4=t1<<1; in dradf4()
185 tr2=cc[t3]+cc[t4]; in dradf4()
189 ch[(t5+=(ido<<1))-1]=cc[t3]-cc[t4]; in dradf4()
195 t4+=ido; in dradf4()
[all …]
/external/libjpeg-turbo/simd/mips/
Djsimd_dspr2.S57 sll t4, a3, 2
58 lwx t5, t4(t5) // t5 = outptr = output_buf[ci][output_row]
70 addu t4, t2, s0
71 addu t7, t4, s0
74 lbu t4, 0(t4)
79 sb t4, -3(t5)
99 sll t4, a3, 2
100 lwx t5, t4(t5) // t5 = outptr = output_buf[ci][output_row]
106 addu t4, t2, s0
107 addu t7, t4, s0
[all …]
/external/deqp-deps/glslang/Test/baseResults/
Dspv.bufferhandle3.frag.out17 Name 9 "t4"
18 MemberName 9(t4) 0 "j"
19 MemberName 9(t4) 1 "k"
28 Name 38 "t4"
29 MemberName 38(t4) 0 "j"
30 MemberName 38(t4) 1 "k"
33 MemberDecorate 9(t4) 0 Offset 0
34 MemberDecorate 9(t4) 1 Offset 8
35 Decorate 9(t4) Block
43 MemberDecorate 38(t4) 0 Offset 0
[all …]
Dspv.bufferhandle4.frag.out17 Name 8 "t4"
18 MemberName 8(t4) 0 "j"
19 MemberName 8(t4) 1 "k"
23 Name 11 "t4"
24 MemberName 11(t4) 0 "j"
25 MemberName 11(t4) 1 "k"
31 MemberDecorate 8(t4) 0 Offset 0
32 MemberDecorate 8(t4) 1 Offset 8
33 Decorate 8(t4) Block
37 MemberDecorate 11(t4) 0 Offset 0
[all …]
Dspv.bufferhandle5.frag.out16 Name 8 "t4"
17 MemberName 8(t4) 0 "j"
18 MemberName 8(t4) 1 "k"
22 MemberDecorate 8(t4) 0 Offset 0
23 MemberDecorate 8(t4) 1 Offset 8
24 Decorate 8(t4) Block
33 8(t4): TypeStruct 6(int) 7
36 10: TypePointer Uniform 8(t4)
/external/swiftshader/third_party/LLVM/test/CodeGen/MSP430/
Dbit.ll39 %t4 = zext i1 %t3 to i8
40 ret i8 %t4
49 %t4 = zext i1 %t3 to i8
50 ret i8 %t4
59 %t4 = zext i1 %t3 to i8
60 ret i8 %t4
69 %t4 = zext i1 %t3 to i8
70 ret i8 %t4
79 %t4 = icmp ne i8 %t3, 0
80 %t5 = zext i1 %t4 to i8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MSP430/
Dbit.ll39 %t4 = zext i1 %t3 to i8
40 ret i8 %t4
49 %t4 = zext i1 %t3 to i8
50 ret i8 %t4
59 %t4 = zext i1 %t3 to i8
60 ret i8 %t4
69 %t4 = zext i1 %t3 to i8
70 ret i8 %t4
79 %t4 = icmp ne i8 %t3, 0
80 %t5 = zext i1 %t4 to i8
[all …]
/external/llvm/test/CodeGen/MSP430/
Dbit.ll39 %t4 = zext i1 %t3 to i8
40 ret i8 %t4
49 %t4 = zext i1 %t3 to i8
50 ret i8 %t4
59 %t4 = zext i1 %t3 to i8
60 ret i8 %t4
69 %t4 = zext i1 %t3 to i8
70 ret i8 %t4
79 %t4 = icmp ne i8 %t3, 0
80 %t5 = zext i1 %t4 to i8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dsplit-store.ll14 %t4 = or i64 %t2, %t3
15 store i64 %t4, i64* %ref.tmp, align 8
29 %t4 = or i64 %t2, %t3
30 store i64 %t4, i64* %ref.tmp, align 8
45 %t4 = or i64 %t2, %t3
46 store i64 %t4, i64* %ref.tmp, align 8
61 %t4 = or i64 %t2, %t3
62 store i64 %t4, i64* %ref.tmp, align 8
75 %t4 = or i64 %t2, %t3
76 store i64 %t4, i64* %ref.tmp, align 8
[all …]
Dfmf-propagation.ll8 ; CHECK: t5: f32 = fadd nsz t2, t4
9 ; CHECK-NEXT: t6: f32 = fadd arcp t5, t4
10 ; CHECK-NEXT: t7: f32 = fadd nnan t6, t4
11 ; CHECK-NEXT: t8: f32 = fadd ninf t7, t4
12 ; CHECK-NEXT: t9: f32 = fadd contract t8, t4
13 ; CHECK-NEXT: t10: f32 = fadd afn t9, t4
14 ; CHECK-NEXT: t11: f32 = fadd reassoc t10, t4
15 ; CHECK-NEXT: t12: f32 = fadd nnan ninf nsz arcp contract afn reassoc t11, t4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
Drv64i-aliases-valid.s96 # CHECK-EXPAND: lui t4, 583
97 # CHECK-EXPAND: addiw t4, t4, -1875
98 # CHECK-EXPAND: slli t4, t4, 14
99 # CHECK-EXPAND: addi t4, t4, -947
100 # CHECK-EXPAND: slli t4, t4, 12
101 # CHECK-EXPAND: addi t4, t4, 1511
102 # CHECK-EXPAND: slli t4, t4, 13
103 # CHECK-EXPAND: addi t4, t4, -272
104 li t4, 0x123456789abcdef0
Drv64c-aliases-valid.s86 # CHECK-EXPAND: lui t4, 583
87 # CHECK-EXPAND: addiw t4, t4, -1875
88 # CHECK-EXPAND: c.slli t4, 14
89 # CHECK-EXPAND: addi t4, t4, -947
90 # CHECK-EXPAND: c.slli t4, 12
91 # CHECK-EXPAND: addi t4, t4, 1511
92 # CHECK-EXPAND: c.slli t4, 13
93 # CHECK-EXPAND: addi t4, t4, -272
94 li t4, 0x123456789abcdef0
/external/libchrome/base/
Dtuple_unittest.cc43 std::tuple<int, int, int, int*> t4(1, 2, 3, &std::get<0>(t1)); in TEST() local
44 std::tuple<int, int, int, int, int*> t5(1, 2, 3, 4, &std::get<0>(t4)); in TEST()
45 std::tuple<int, int, int, int, int, int*> t6(1, 2, 3, 4, 5, &std::get<0>(t4)); in TEST()
48 DispatchToFunction(&DoAdd, t4); in TEST()
56 EXPECT_EQ(1, std::get<0>(t4)); in TEST()
58 EXPECT_EQ(10, std::get<0>(t4)); in TEST()
61 EXPECT_EQ(10, std::get<0>(t4)); in TEST()
63 EXPECT_EQ(15, std::get<0>(t4)); in TEST()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopStrengthReduce/
Duglygep-address-space.ll20 %t = add i16 %t4, 1 ; <i16> [#uses=1]
24 %t4 = phi i16 [ %t, %bb2 ], [ 0, %bb ] ; <i16> [#uses=3]
28 ; CHECK-NEXT: %t7 = icmp eq i16 %t4, 0
30 ; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* undef, i16 %t4
33 %t7 = icmp eq i16 %t4, 0 ; <i1> [#uses=1]
34 %t3 = add i16 %t4, 16 ; <i16> [#uses=1]
43 ; Use the induction variable (%t4) to access the right element
44 ; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
48 %t2 = getelementptr inbounds i8, i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
Daddress-space-loop.ll20 %t = add i16 %t4, 1 ; <i16> [#uses=1]
24 %t4 = phi i16 [ %t, %bb2 ], [ 0, %bb ] ; <i16> [#uses=3]
28 ; CHECK-NEXT: %t7 = icmp eq i16 %t4, 0
30 ; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* undef, i16 %t4
33 %t7 = icmp eq i16 %t4, 0 ; <i1> [#uses=1]
34 %t3 = add i16 %t4, 16 ; <i16> [#uses=1]
43 ; Use the induction variable (%t4) to access the right element
44 ; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
48 %t2 = getelementptr inbounds i8, i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
/external/llvm/test/Transforms/LoopStrengthReduce/
Daddress-space-loop.ll20 %t = add i16 %t4, 1 ; <i16> [#uses=1]
24 %t4 = phi i16 [ %t, %bb2 ], [ 0, %bb ] ; <i16> [#uses=3]
28 ; CHECK-NEXT: %t7 = icmp eq i16 %t4, 0
30 ; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* undef, i16 %t4
33 %t7 = icmp eq i16 %t4, 0 ; <i1> [#uses=1]
34 %t3 = add i16 %t4, 16 ; <i16> [#uses=1]
43 ; Use the induction variable (%t4) to access the right element
44 ; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
48 %t2 = getelementptr inbounds i8, i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
Duglygep-address-space.ll20 %t = add i16 %t4, 1 ; <i16> [#uses=1]
24 %t4 = phi i16 [ %t, %bb2 ], [ 0, %bb ] ; <i16> [#uses=3]
28 ; CHECK-NEXT: %t7 = icmp eq i16 %t4, 0
30 ; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* undef, i16 %t4
33 %t7 = icmp eq i16 %t4, 0 ; <i1> [#uses=1]
34 %t3 = add i16 %t4, 16 ; <i16> [#uses=1]
43 ; Use the induction variable (%t4) to access the right element
44 ; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
48 %t2 = getelementptr inbounds i8, i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
/external/clang/test/CXX/except/except.spec/
Dp5-pointers.cpp48 void (*t4)() throw(A) = &s1; // valid in fnptrs()
49 t4 = &s3; // valid in fnptrs()
50 t4 = &s4; // valid in fnptrs()
51 …t4 = &s5; // expected-error {{not superset}} expected-error {{incompatible ty… in fnptrs()
59 …t6 = t4; // expected-error {{not superset}} expected-error {{incompatible ty… in fnptrs()
60 t4 = t6; // valid in fnptrs()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dsigned-comparison.ll6 define i1 @scalar_zext_slt(i16 %t4) {
8 ; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 %t4, 500
11 %t5 = zext i16 %t4 to i32
16 define <4 x i1> @vector_zext_slt(<4 x i16> %t4) {
18 ; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> %t4, <i16 500, i16 0, i16 501, i16 -1>
21 %t5 = zext <4 x i16> %t4 to <4 x i32>
/external/llvm/test/Transforms/InstCombine/
Dsigned-comparison.ll6 define i1 @scalar_zext_slt(i16 %t4) {
8 ; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 %t4, 500
11 %t5 = zext i16 %t4 to i32
16 define <4 x i1> @vector_zext_slt(<4 x i16> %t4) {
18 ; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> %t4, <i16 500, i16 0, i16 501, i16 -1>
21 %t5 = zext <4 x i16> %t4 to <4 x i32>
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dmasked-iv-unsafe.ll22 %t4 = load double* %t3
23 %t5 = fmul double %t4, 2.3
50 %t4 = load double* %t3
51 %t5 = fmul double %t4, 2.3
80 %t4 = load double* %t3
81 %t5 = fmul double %t4, 2.3
110 %t4 = load double* %t3
111 %t5 = fmul double %t4, 2.3
138 %t4 = load double* %t3
139 %t5 = fmul double %t4, 2.3
[all …]

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