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/external/libjpeg-turbo/simd/mips/
Djsimd_dspr2.S71 addu t7, t4, s0
72 addu t8, t7, s0
75 lbu t7, 0(t7)
80 sb t7, -2(t5)
107 addu t7, t4, s0
108 addu t8, t7, s0
111 lbu t7, 0(t7)
116 sb t7, -2(t5)
166 lw t7, 48(sp) // t7 = num_rows
178 addiu t7, -1 // --num_rows
[all …]
/external/llvm/test/CodeGen/X86/
Dcrash-lre-eliminate-dead-def.ll60 %t7.0 = phi i16 [ undef, %entry ], [ %t7.1, %for.end29 ], [ %t7.19, %cleanup100 ]
94 %t7.1 = phi i16 [ %t7.2, %for.cond17 ], [ %t7.0, %if.end11 ]
100 %t7.2 = phi i16 [ %t7.3, %for.cond20 ], [ %t7.1, %for.cond15 ]
106 %t7.3 = phi i16 [ %t7.4, %for.cond23 ], [ %t7.2, %for.cond17 ]
111 %t7.4 = phi i16 [ %t7.5, %L1 ], [ %t7.3, %for.cond20 ]
116 %t7.5 = phi i16 [ %t7.19, %cleanup100 ], [ %t7.4, %for.cond23 ]
128 %t7.6 = phi i16 [ %t7.1, %for.cond32thread-pre-split ], [ %t7.17, %for.inc94 ]
150 %t7.7 = phi i16 [ %tmp5, %if.then38 ], [ %t7.15, %while.end.split ]
166 %t7.9 = phi i16 [ %t7.7, %if.end48 ], [ %.130, %for.cond52.preheader ]
175 %t7.10 = phi i16 [ %t7.19, %cleanup100.L5_crit_edge ], [ %t7.9, %if.then63 ], [ %t7.0, %if.end11 ]
[all …]
Dmasked-iv-unsafe.ll26 %t7 = load double, double* %t6
27 %t8 = fmul double %t7, 4.5
54 %t7 = load double, double* %t6
55 %t8 = fmul double %t7, 4.5
84 %t7 = load double, double* %t6
85 %t8 = fmul double %t7, 4.5
114 %t7 = load double, double* %t6
115 %t8 = fmul double %t7, 4.5
142 %t7 = load double, double* %t6
143 %t8 = fmul double %t7, 4.5
[all …]
Dmasked-iv-safe.ll28 %t7 = load double, double* %t6
29 %t8 = fmul double %t7, 4.5
61 %t7 = load double, double* %t6
62 %t8 = fmul double %t7, 4.5
96 %t7 = load double, double* %t6
97 %t8 = fmul double %t7, 4.5
131 %t7 = load double, double* %t6
132 %t8 = fmul double %t7, 4.5
164 %t7 = load double, double* %t6
165 %t8 = fmul double %t7, 4.5
[all …]
Dvec_ins_extract-1.ll8 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
29 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
34 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
58 %t9 = extractelement <4 x i32> %t13, i32 %t7
62 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
81 %t9 = extractelement <4 x i32> %t8, i32 %t7
86 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
108 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dcrash-lre-eliminate-dead-def.ll60 %t7.0 = phi i16 [ undef, %entry ], [ %t7.1, %for.end29 ], [ %t7.19, %cleanup100 ]
94 %t7.1 = phi i16 [ %t7.2, %for.cond17 ], [ %t7.0, %if.end11 ]
100 %t7.2 = phi i16 [ %t7.3, %for.cond20 ], [ %t7.1, %for.cond15 ]
106 %t7.3 = phi i16 [ %t7.4, %for.cond23 ], [ %t7.2, %for.cond17 ]
111 %t7.4 = phi i16 [ %t7.5, %L1 ], [ %t7.3, %for.cond20 ]
116 %t7.5 = phi i16 [ %t7.19, %cleanup100 ], [ %t7.4, %for.cond23 ]
128 %t7.6 = phi i16 [ %t7.1, %for.cond32thread-pre-split ], [ %t7.17, %for.inc94 ]
150 %t7.7 = phi i16 [ %tmp5, %if.then38 ], [ %t7.15, %while.end.split ]
166 %t7.9 = phi i16 [ %t7.7, %if.end48 ], [ %.130, %for.cond52.preheader ]
175 %t7.10 = phi i16 [ %t7.19, %cleanup100.L5_crit_edge ], [ %t7.9, %if.then63 ], [ %t7.0, %if.end11 ]
[all …]
Dmasked-iv-unsafe.ll26 %t7 = load double, double* %t6
27 %t8 = fmul double %t7, 4.5
54 %t7 = load double, double* %t6
55 %t8 = fmul double %t7, 4.5
84 %t7 = load double, double* %t6
85 %t8 = fmul double %t7, 4.5
114 %t7 = load double, double* %t6
115 %t8 = fmul double %t7, 4.5
142 %t7 = load double, double* %t6
143 %t8 = fmul double %t7, 4.5
[all …]
Dmasked-iv-safe.ll28 %t7 = load double, double* %t6
29 %t8 = fmul double %t7, 4.5
61 %t7 = load double, double* %t6
62 %t8 = fmul double %t7, 4.5
96 %t7 = load double, double* %t6
97 %t8 = fmul double %t7, 4.5
131 %t7 = load double, double* %t6
132 %t8 = fmul double %t7, 4.5
164 %t7 = load double, double* %t6
165 %t8 = fmul double %t7, 4.5
[all …]
Dvec_ins_extract-1.ll8 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
31 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
36 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
62 %t9 = extractelement <4 x i32> %t13, i32 %t7
66 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
87 %t9 = extractelement <4 x i32> %t8, i32 %t7
92 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
116 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
/external/libaom/libaom/av1/common/arm/
Dwiener_convolve_neon.c81 uint8x8_t t0, t1, t2, t3, t4, t5, t6, t7; in av1_wiener_convolve_add_src_neon() local
98 load_u8_8x8(src_ptr, src_stride, &t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in av1_wiener_convolve_add_src_neon()
99 transpose_u8_8x8(&t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in av1_wiener_convolve_add_src_neon()
115 load_u8_8x8(s, src_stride, &t7, &t8, &t9, &t10, &t11, &t12, &t13, &t14); in av1_wiener_convolve_add_src_neon()
116 transpose_u8_8x8(&t7, &t8, &t9, &t10, &t11, &t12, &t13, &t14); in av1_wiener_convolve_add_src_neon()
125 res0 = vreinterpretq_s16_u16(vaddl_u8(t1, t7)); in av1_wiener_convolve_add_src_neon()
133 res1 = vreinterpretq_s16_u16(vaddl_u8(t3, t7)); in av1_wiener_convolve_add_src_neon()
141 res2 = vreinterpretq_s16_u16(vaddl_u8(t5, t7)); in av1_wiener_convolve_add_src_neon()
149 res3 = vreinterpretq_s16_u16(vmovl_u8(t7)); in av1_wiener_convolve_add_src_neon()
155 res2 = vreinterpretq_s16_u16(vaddl_u8(t7, t9)); in av1_wiener_convolve_add_src_neon()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dvec_ins_extract-1.ll6 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
7 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
11 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
13 %t9 = extractelement <4 x i32> %t13, i32 %t7
16 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
17 %t9 = extractelement <4 x i32> %t8, i32 %t7
21 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
23 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
Dmasked-iv-unsafe.ll26 %t7 = load double* %t6
27 %t8 = fmul double %t7, 4.5
54 %t7 = load double* %t6
55 %t8 = fmul double %t7, 4.5
84 %t7 = load double* %t6
85 %t8 = fmul double %t7, 4.5
114 %t7 = load double* %t6
115 %t8 = fmul double %t7, 4.5
142 %t7 = load double* %t6
143 %t8 = fmul double %t7, 4.5
[all …]
Dmasked-iv-safe.ll31 %t7 = load double* %t6
32 %t8 = fmul double %t7, 4.5
59 %t7 = load double* %t6
60 %t8 = fmul double %t7, 4.5
89 %t7 = load double* %t6
90 %t8 = fmul double %t7, 4.5
119 %t7 = load double* %t6
120 %t8 = fmul double %t7, 4.5
147 %t7 = load double* %t6
148 %t8 = fmul double %t7, 4.5
[all …]
/external/speex/libspeexdsp/
Dsmallft.c278 int t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10; in dradfg() local
424 t7=idl1; in dradfg()
427 ch2[t4++]=c2[ik]+ar1*c2[t7++]; in dradfg()
447 t7=t2; in dradfg()
452 ch2[t7++]+=ai2*c2[t9++]; in dradfg()
502 t7=t4; in dradfg()
506 cc[t5]=ch[t7]; in dradfg()
509 t7+=ido; in dradfg()
526 t7=t3; in dradfg()
532 cc[i+t7-1]=ch[i+t8-1]+ch[i+t9-1]; in dradfg()
[all …]
/external/python/cpython3/Lib/test/
Dtest_pkg.py257 t7, sub, subsub = None, None, None
258 import t7 as tas
262 self.assertFalse(t7)
263 from t7 import sub as subpar
267 self.assertFalse(t7)
269 from t7.sub import subsub as subsubsub
274 self.assertFalse(t7)
277 from t7.sub.subsub import spam as ham
279 self.assertFalse(t7)
/external/compiler-rt/lib/sanitizer_common/tests/
Dsanitizer_bvgraph_test.cc270 BV t7; in ShortestPath() local
271 t7.clear(); in ShortestPath()
272 t7.setBit(7); in ShortestPath()
282 EXPECT_TRUE(g.isReachable(1, t7)); in ShortestPath()
284 EXPECT_EQ(0U, g.findPath(1, t7, path, 1)); in ShortestPath()
286 EXPECT_EQ(2U, g.findPath(1, t7, path, 2)); in ShortestPath()
287 EXPECT_EQ(2U, g.findPath(1, t7, path, 3)); in ShortestPath()
288 EXPECT_EQ(2U, g.findPath(1, t7, path, 4)); in ShortestPath()
289 EXPECT_EQ(2U, g.findPath(1, t7, path, 5)); in ShortestPath()
290 EXPECT_EQ(2U, g.findPath(1, t7, path, 6)); in ShortestPath()
[all …]
/external/python/cpython2/Lib/test/
Dtest_pkg.py250 t7, sub, subsub = None, None, None
251 import t7 as tas
255 self.assertFalse(t7)
256 from t7 import sub as subpar
260 self.assertFalse(t7)
262 from t7.sub import subsub as subsubsub
266 self.assertFalse(t7)
269 from t7.sub.subsub import spam as ham
271 self.assertFalse(t7)
/external/llvm/test/MC/Mips/
Dmips64-register-names-n32-n64.s30 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
35 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
40 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
45 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
46 # WARNING-NEXT: daddiu $t7, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0f,0x00,0x00]
49 daddiu $t7, $zero, 0 # CHECK: encoding: [0x64,0x0f,0x00,0x00]
68 # [*] - t0-t3 are aliases of t4-t7 for compatibility with both the original
69 # ABI documentation (using t4-t7) and GNU As (using t0-t3)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LICM/
Dloopsink.ll34 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
61 %t7 = add nuw nsw i32 %iv, 1
62 %c7 = icmp eq i32 %t7, %p7
101 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
128 %t7 = add nuw nsw i32 %iv, 1
129 %c7 = icmp eq i32 %t7, %p7
163 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
190 %t7 = add nuw nsw i32 %iv, 1
191 %c7 = icmp eq i32 %t7, %p7
248 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmips64-register-names-n32-n64.s31 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
36 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
41 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
46 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
47 # WARNING-NEXT: daddiu $t7, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0f,0x00,0x00]
50 daddiu $t7, $zero, 0 # CHECK: encoding: [0x64,0x0f,0x00,0x00]
69 # [*] - t0-t3 are aliases of t4-t7 for compatibility with both the original
70 # ABI documentation (using t4-t7) and GNU As (using t0-t3)
/external/v8/src/mips/
Dcodegen-mips.cc143 __ lw(t7, MemOperand(a1, 7, loadstore_chunk)); in CreateMemCopyUint8Function()
153 __ sw(t7, MemOperand(a0, 7, loadstore_chunk)); in CreateMemCopyUint8Function()
162 __ lw(t7, MemOperand(a1, 15, loadstore_chunk)); in CreateMemCopyUint8Function()
172 __ sw(t7, MemOperand(a0, 15, loadstore_chunk)); in CreateMemCopyUint8Function()
193 __ lw(t7, MemOperand(a1, 7, loadstore_chunk)); in CreateMemCopyUint8Function()
202 __ sw(t7, MemOperand(a0, 7, loadstore_chunk)); in CreateMemCopyUint8Function()
307 __ lwr(t7, MemOperand(a1, 7, loadstore_chunk)); in CreateMemCopyUint8Function()
322 __ lwl(t7, in CreateMemCopyUint8Function()
342 __ lwl(t7, MemOperand(a1, 7, loadstore_chunk)); in CreateMemCopyUint8Function()
357 __ lwr(t7, in CreateMemCopyUint8Function()
[all …]
/external/openssh/regress/
DMakefile3 REGRESS_TARGETS= unit t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t-exec
114 t6.out1 t6.out2 t7.out t7.out.pub t8.out t8.out.pub \
156 $(OBJ)/t7.out:
159 t7: $(OBJ)/t7.out target
160 ${TEST_SSH_SSHKEYGEN} -lf $(OBJ)/t7.out > /dev/null
161 ${TEST_SSH_SSHKEYGEN} -Bf $(OBJ)/t7.out > /dev/null
/external/libvpx/libvpx/vpx_dsp/arm/
Dvpx_convolve8_neon.c154 uint8x8_t t4, t5, t6, t7; in vpx_convolve8_horiz_neon() local
159 load_u8_8x8(src, src_stride, &t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in vpx_convolve8_horiz_neon()
160 transpose_u8_8x8(&t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in vpx_convolve8_horiz_neon()
170 &t7); in vpx_convolve8_horiz_neon()
180 transpose_u8_4x8(&t0, &t1, &t2, &t3, t4, t5, t6, t7); in vpx_convolve8_horiz_neon()
235 load_u8_8x8(src, src_stride, &t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in vpx_convolve8_horiz_neon()
236 transpose_u8_8x8(&t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in vpx_convolve8_horiz_neon()
258 load_u8_8x8(s, src_stride, &t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in vpx_convolve8_horiz_neon()
259 transpose_u8_8x8(&t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in vpx_convolve8_horiz_neon()
267 s14 = vreinterpretq_s16_u16(vmovl_u8(t7)); in vpx_convolve8_horiz_neon()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dselect-imm.ll159 define i32 @t7(i32 %a, i32 %b) nounwind readnone {
161 ; ARM-LABEL: t7:
166 ; ARMT2-LABEL: t7:
171 ; THUMB1-LABEL: t7:
177 ; THUMB2-LABEL: t7:
193 ; ARMT2: bl t7
200 ; THUMB1: bl t7
208 ; THUMB2: bl t7
216 %call = tail call i32 @t7(i32 9, i32 %a)
217 tail call i32 @t7(i32 %conv, i32 %call)
/external/llvm/test/Transforms/Reassociate/
Dmightymul.ll12 %t7 = mul i32 %t6, %t6
13 %t8 = mul i32 %t7, %t7

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