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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * cpu.h
4  *
5  * AM33xx specific header file
6  *
7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8  */
9 
10 #ifndef _AM33XX_CPU_H
11 #define _AM33XX_CPU_H
12 
13 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
14 #include <asm/types.h>
15 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
16 
17 #include <asm/arch/hardware.h>
18 
19 #define CL_BIT(x)			(0 << x)
20 
21 /* Timer register bits */
22 #define TCLR_ST				BIT(0)	/* Start=1 Stop=0 */
23 #define TCLR_AR				BIT(1)	/* Auto reload */
24 #define TCLR_PRE			BIT(5)	/* Pre-scaler enable */
25 #define TCLR_PTV_SHIFT			(2)	/* Pre-scaler shift value */
26 #define TCLR_PRE_DISABLE		CL_BIT(5) /* Pre-scalar disable */
27 #define TCLR_CE				BIT(6)	/* compare mode enable */
28 #define TCLR_SCPWM			BIT(7)	/* pwm outpin behaviour */
29 #define TCLR_TCM			BIT(8)	/* edge detection of input pin*/
30 #define TCLR_TRG_SHIFT			(10)	/* trigmode on pwm outpin */
31 #define TCLR_PT				BIT(12)	/* pulse/toggle mode of outpin*/
32 #define TCLR_CAPTMODE			BIT(13) /* capture mode */
33 #define TCLR_GPOCFG			BIT(14)	/* 0=output,1=input */
34 
35 #define TCFG_RESET			BIT(0)	/* software reset */
36 #define TCFG_EMUFREE			BIT(1)	/* behaviour of tmr on debug */
37 #define TCFG_IDLEMOD_SHIFT		(2)	/* power management */
38 
39 /* cpu-id for AM43XX AM33XX and TI81XX family */
40 #define AM437X				0xB98C
41 #define AM335X				0xB944
42 #define TI81XX				0xB81E
43 #define DEVICE_ID			(CTRL_BASE + 0x0600)
44 #define DEVICE_ID_MASK			0x1FFF
45 #define PACKAGE_TYPE_SHIFT		16
46 #define PACKAGE_TYPE_MASK		(3 << 16)
47 
48 /* Package Type */
49 #define PACKAGE_TYPE_UNDEFINED		0x0
50 #define PACKAGE_TYPE_ZCZ		0x1
51 #define PACKAGE_TYPE_ZCE		0x2
52 #define PACKAGE_TYPE_RESERVED		0x3
53 
54 /* MPU max frequencies */
55 #define AM335X_ZCZ_300			0x1FEF
56 #define AM335X_ZCZ_600			0x1FAF
57 #define AM335X_ZCZ_720			0x1F2F
58 #define AM335X_ZCZ_800			0x1E2F
59 #define AM335X_ZCZ_1000			0x1C2F
60 #define AM335X_ZCE_300			0x1FDF
61 #define AM335X_ZCE_600			0x1F9F
62 
63 /* This gives the status of the boot mode pins on the evm */
64 #define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
65 					| BIT(3) | BIT(4))
66 
67 #define PRM_RSTCTRL_RESET		0x01
68 #define PRM_RSTST_WARM_RESET_MASK	0x232
69 
70 /* EMIF Control register bits */
71 #define EMIF_CTRL_DEVOFF	BIT(0)
72 
73 #ifndef __KERNEL_STRICT_NAMES
74 #ifndef __ASSEMBLY__
75 #include <asm/ti-common/omap_wdt.h>
76 
77 #ifndef CONFIG_AM43XX
78 /* Encapsulating core pll registers */
79 struct cm_wkuppll {
80 	unsigned int wkclkstctrl;	/* offset 0x00 */
81 	unsigned int wkctrlclkctrl;	/* offset 0x04 */
82 	unsigned int wkgpio0clkctrl;	/* offset 0x08 */
83 	unsigned int wkl4wkclkctrl;	/* offset 0x0c */
84 	unsigned int timer0clkctrl;	/* offset 0x10 */
85 	unsigned int resv2[3];
86 	unsigned int idlestdpllmpu;	/* offset 0x20 */
87 	unsigned int sscdeltamstepdllmpu; /* off  0x24 */
88 	unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
89 	unsigned int clkseldpllmpu;	/* offset 0x2c */
90 	unsigned int resv4[1];
91 	unsigned int idlestdpllddr;	/* offset 0x34 */
92 	unsigned int resv5[2];
93 	unsigned int clkseldpllddr;	/* offset 0x40 */
94 	unsigned int resv6[4];
95 	unsigned int clkseldplldisp;	/* offset 0x54 */
96 	unsigned int resv7[1];
97 	unsigned int idlestdpllcore;	/* offset 0x5c */
98 	unsigned int resv8[2];
99 	unsigned int clkseldpllcore;	/* offset 0x68 */
100 	unsigned int resv9[1];
101 	unsigned int idlestdpllper;	/* offset 0x70 */
102 	unsigned int resv10[2];
103 	unsigned int clkdcoldodpllper;	/* offset 0x7c */
104 	unsigned int divm4dpllcore;	/* offset 0x80 */
105 	unsigned int divm5dpllcore;	/* offset 0x84 */
106 	unsigned int clkmoddpllmpu;	/* offset 0x88 */
107 	unsigned int clkmoddpllper;	/* offset 0x8c */
108 	unsigned int clkmoddpllcore;	/* offset 0x90 */
109 	unsigned int clkmoddpllddr;	/* offset 0x94 */
110 	unsigned int clkmoddplldisp;	/* offset 0x98 */
111 	unsigned int clkseldpllper;	/* offset 0x9c */
112 	unsigned int divm2dpllddr;	/* offset 0xA0 */
113 	unsigned int divm2dplldisp;	/* offset 0xA4 */
114 	unsigned int divm2dpllmpu;	/* offset 0xA8 */
115 	unsigned int divm2dpllper;	/* offset 0xAC */
116 	unsigned int resv11[1];
117 	unsigned int wkup_uart0ctrl;	/* offset 0xB4 */
118 	unsigned int wkup_i2c0ctrl;	/* offset 0xB8 */
119 	unsigned int wkup_adctscctrl;	/* offset 0xBC */
120 	unsigned int resv12;
121 	unsigned int timer1clkctrl;	/* offset 0xC4 */
122 	unsigned int resv13[4];
123 	unsigned int divm6dpllcore;	/* offset 0xD8 */
124 };
125 
126 /**
127  * Encapsulating peripheral functional clocks
128  * pll registers
129  */
130 struct cm_perpll {
131 	unsigned int l4lsclkstctrl;	/* offset 0x00 */
132 	unsigned int l3sclkstctrl;	/* offset 0x04 */
133 	unsigned int l4fwclkstctrl;	/* offset 0x08 */
134 	unsigned int l3clkstctrl;	/* offset 0x0c */
135 	unsigned int resv1;
136 	unsigned int cpgmac0clkctrl;	/* offset 0x14 */
137 	unsigned int lcdclkctrl;	/* offset 0x18 */
138 	unsigned int usb0clkctrl;	/* offset 0x1C */
139 	unsigned int resv2;
140 	unsigned int tptc0clkctrl;	/* offset 0x24 */
141 	unsigned int emifclkctrl;	/* offset 0x28 */
142 	unsigned int ocmcramclkctrl;	/* offset 0x2c */
143 	unsigned int gpmcclkctrl;	/* offset 0x30 */
144 	unsigned int mcasp0clkctrl;	/* offset 0x34 */
145 	unsigned int uart5clkctrl;	/* offset 0x38 */
146 	unsigned int mmc0clkctrl;	/* offset 0x3C */
147 	unsigned int elmclkctrl;	/* offset 0x40 */
148 	unsigned int i2c2clkctrl;	/* offset 0x44 */
149 	unsigned int i2c1clkctrl;	/* offset 0x48 */
150 	unsigned int spi0clkctrl;	/* offset 0x4C */
151 	unsigned int spi1clkctrl;	/* offset 0x50 */
152 	unsigned int resv3[3];
153 	unsigned int l4lsclkctrl;	/* offset 0x60 */
154 	unsigned int l4fwclkctrl;	/* offset 0x64 */
155 	unsigned int mcasp1clkctrl;	/* offset 0x68 */
156 	unsigned int uart1clkctrl;	/* offset 0x6C */
157 	unsigned int uart2clkctrl;	/* offset 0x70 */
158 	unsigned int uart3clkctrl;	/* offset 0x74 */
159 	unsigned int uart4clkctrl;	/* offset 0x78 */
160 	unsigned int timer7clkctrl;	/* offset 0x7C */
161 	unsigned int timer2clkctrl;	/* offset 0x80 */
162 	unsigned int timer3clkctrl;	/* offset 0x84 */
163 	unsigned int timer4clkctrl;	/* offset 0x88 */
164 	unsigned int resv4[8];
165 	unsigned int gpio1clkctrl;	/* offset 0xAC */
166 	unsigned int gpio2clkctrl;	/* offset 0xB0 */
167 	unsigned int gpio3clkctrl;	/* offset 0xB4 */
168 	unsigned int resv5;
169 	unsigned int tpccclkctrl;	/* offset 0xBC */
170 	unsigned int dcan0clkctrl;	/* offset 0xC0 */
171 	unsigned int dcan1clkctrl;	/* offset 0xC4 */
172 	unsigned int resv6;
173 	unsigned int epwmss1clkctrl;	/* offset 0xCC */
174 	unsigned int emiffwclkctrl;	/* offset 0xD0 */
175 	unsigned int epwmss0clkctrl;	/* offset 0xD4 */
176 	unsigned int epwmss2clkctrl;	/* offset 0xD8 */
177 	unsigned int l3instrclkctrl;	/* offset 0xDC */
178 	unsigned int l3clkctrl;		/* Offset 0xE0 */
179 	unsigned int resv8[2];
180 	unsigned int timer5clkctrl;	/* offset 0xEC */
181 	unsigned int timer6clkctrl;	/* offset 0xF0 */
182 	unsigned int mmc1clkctrl;	/* offset 0xF4 */
183 	unsigned int mmc2clkctrl;	/* offset 0xF8 */
184 	unsigned int resv9[8];
185 	unsigned int l4hsclkstctrl;	/* offset 0x11C */
186 	unsigned int l4hsclkctrl;	/* offset 0x120 */
187 	unsigned int resv10[8];
188 	unsigned int cpswclkstctrl;	/* offset 0x144 */
189 	unsigned int lcdcclkstctrl;	/* offset 0x148 */
190 };
191 
192 /* Encapsulating Display pll registers */
193 struct cm_dpll {
194 	unsigned int resv1;
195 	unsigned int clktimer7clk;	/* offset 0x04 */
196 	unsigned int clktimer2clk;	/* offset 0x08 */
197 	unsigned int clktimer3clk;	/* offset 0x0C */
198 	unsigned int clktimer4clk;	/* offset 0x10 */
199 	unsigned int resv2;
200 	unsigned int clktimer5clk;	/* offset 0x18 */
201 	unsigned int clktimer6clk;	/* offset 0x1C */
202 	unsigned int resv3[2];
203 	unsigned int clktimer1clk;	/* offset 0x28 */
204 	unsigned int resv4[2];
205 	unsigned int clklcdcpixelclk;	/* offset 0x34 */
206 };
207 
208 struct prm_device_inst {
209 	unsigned int prm_rstctrl;
210 	unsigned int prm_rsttime;
211 	unsigned int prm_rstst;
212 };
213 #else
214 /* Encapsulating core pll registers */
215 struct cm_wkuppll {
216 	unsigned int resv0[136];
217 	unsigned int wkl4wkclkctrl;	/* offset 0x220 */
218 	unsigned int resv1[7];
219 	unsigned int usbphy0clkctrl;	/* offset 0x240 */
220 	unsigned int resv112;
221 	unsigned int usbphy1clkctrl;	/* offset 0x248 */
222 	unsigned int resv113[45];
223 	unsigned int wkclkstctrl;	/* offset 0x300 */
224 	unsigned int resv2[15];
225 	unsigned int wkup_i2c0ctrl;	/* offset 0x340 */
226 	unsigned int resv3;
227 	unsigned int wkup_uart0ctrl;	/* offset 0x348 */
228 	unsigned int resv4[5];
229 	unsigned int wkctrlclkctrl;	/* offset 0x360 */
230 	unsigned int resv5;
231 	unsigned int wkgpio0clkctrl;	/* offset 0x368 */
232 
233 	unsigned int resv6[109];
234 	unsigned int clkmoddpllcore;	/* offset 0x520 */
235 	unsigned int idlestdpllcore;	/* offset 0x524 */
236 	unsigned int resv61;
237 	unsigned int clkseldpllcore;	/* offset 0x52C */
238 	unsigned int resv7[2];
239 	unsigned int divm4dpllcore;	/* offset 0x538 */
240 	unsigned int divm5dpllcore;	/* offset 0x53C */
241 	unsigned int divm6dpllcore;	/* offset 0x540 */
242 
243 	unsigned int resv8[7];
244 	unsigned int clkmoddpllmpu;	/* offset 0x560 */
245 	unsigned int idlestdpllmpu;	/* offset 0x564 */
246 	unsigned int resv9;
247 	unsigned int clkseldpllmpu;	/* offset 0x56c */
248 	unsigned int divm2dpllmpu;	/* offset 0x570 */
249 
250 	unsigned int resv10[11];
251 	unsigned int clkmoddpllddr;	/* offset 0x5A0 */
252 	unsigned int idlestdpllddr;	/* offset 0x5A4 */
253 	unsigned int resv11;
254 	unsigned int clkseldpllddr;	/* offset 0x5AC */
255 	unsigned int divm2dpllddr;	/* offset 0x5B0 */
256 
257 	unsigned int resv12[11];
258 	unsigned int clkmoddpllper;	/* offset 0x5E0 */
259 	unsigned int idlestdpllper;	/* offset 0x5E4 */
260 	unsigned int resv13;
261 	unsigned int clkseldpllper;	/* offset 0x5EC */
262 	unsigned int divm2dpllper;	/* offset 0x5F0 */
263 	unsigned int resv14[8];
264 	unsigned int clkdcoldodpllper;	/* offset 0x614 */
265 
266 	unsigned int resv15[2];
267 	unsigned int clkmoddplldisp;	/* offset 0x620 */
268 	unsigned int resv16[2];
269 	unsigned int clkseldplldisp;	/* offset 0x62C */
270 	unsigned int divm2dplldisp;	/* offset 0x630 */
271 };
272 
273 /*
274  * Encapsulating peripheral functional clocks
275  * pll registers
276  */
277 struct cm_perpll {
278 	unsigned int l3clkstctrl;	/* offset 0x00 */
279 	unsigned int resv0[7];
280 	unsigned int l3clkctrl;		/* Offset 0x20 */
281 	unsigned int resv112[7];
282 	unsigned int l3instrclkctrl;	/* offset 0x40 */
283 	unsigned int resv2[3];
284 	unsigned int ocmcramclkctrl;	/* offset 0x50 */
285 	unsigned int resv3[9];
286 	unsigned int tpccclkctrl;	/* offset 0x78 */
287 	unsigned int resv4;
288 	unsigned int tptc0clkctrl;	/* offset 0x80 */
289 
290 	unsigned int resv5[7];
291 	unsigned int l4hsclkctrl;	/* offset 0x0A0 */
292 	unsigned int resv6;
293 	unsigned int l4fwclkctrl;	/* offset 0x0A8 */
294 	unsigned int resv7[85];
295 	unsigned int l3sclkstctrl;	/* offset 0x200 */
296 	unsigned int resv8[7];
297 	unsigned int gpmcclkctrl;	/* offset 0x220 */
298 	unsigned int resv9[5];
299 	unsigned int mcasp0clkctrl;	/* offset 0x238 */
300 	unsigned int resv10;
301 	unsigned int mcasp1clkctrl;	/* offset 0x240 */
302 	unsigned int resv11;
303 	unsigned int mmc2clkctrl;	/* offset 0x248 */
304 	unsigned int resv12[3];
305 	unsigned int qspiclkctrl;       /* offset 0x258 */
306 	unsigned int resv121;
307 	unsigned int usb0clkctrl;	/* offset 0x260 */
308 	unsigned int resv122;
309 	unsigned int usb1clkctrl;	/* offset 0x268 */
310 	unsigned int resv13[101];
311 	unsigned int l4lsclkstctrl;	/* offset 0x400 */
312 	unsigned int resv14[7];
313 	unsigned int l4lsclkctrl;	/* offset 0x420 */
314 	unsigned int resv15;
315 	unsigned int dcan0clkctrl;	/* offset 0x428 */
316 	unsigned int resv16;
317 	unsigned int dcan1clkctrl;	/* offset 0x430 */
318 	unsigned int resv17[13];
319 	unsigned int elmclkctrl;	/* offset 0x468 */
320 
321 	unsigned int resv18[3];
322 	unsigned int gpio1clkctrl;	/* offset 0x478 */
323 	unsigned int resv19;
324 	unsigned int gpio2clkctrl;	/* offset 0x480 */
325 	unsigned int resv20;
326 	unsigned int gpio3clkctrl;	/* offset 0x488 */
327 	unsigned int resv41;
328 	unsigned int gpio4clkctrl;	/* offset 0x490 */
329 	unsigned int resv42;
330 	unsigned int gpio5clkctrl;	/* offset 0x498 */
331 	unsigned int resv21[3];
332 
333 	unsigned int i2c1clkctrl;	/* offset 0x4A8 */
334 	unsigned int resv22;
335 	unsigned int i2c2clkctrl;	/* offset 0x4B0 */
336 	unsigned int resv23[3];
337 	unsigned int mmc0clkctrl;	/* offset 0x4C0 */
338 	unsigned int resv24;
339 	unsigned int mmc1clkctrl;	/* offset 0x4C8 */
340 
341 	unsigned int resv25[13];
342 	unsigned int spi0clkctrl;	/* offset 0x500 */
343 	unsigned int resv26;
344 	unsigned int spi1clkctrl;	/* offset 0x508 */
345 	unsigned int resv27[9];
346 	unsigned int timer2clkctrl;	/* offset 0x530 */
347 	unsigned int resv28;
348 	unsigned int timer3clkctrl;	/* offset 0x538 */
349 	unsigned int resv29;
350 	unsigned int timer4clkctrl;	/* offset 0x540 */
351 	unsigned int resv30[5];
352 	unsigned int timer7clkctrl;	/* offset 0x558 */
353 
354 	unsigned int resv31[9];
355 	unsigned int uart1clkctrl;	/* offset 0x580 */
356 	unsigned int resv32;
357 	unsigned int uart2clkctrl;	/* offset 0x588 */
358 	unsigned int resv33;
359 	unsigned int uart3clkctrl;	/* offset 0x590 */
360 	unsigned int resv34;
361 	unsigned int uart4clkctrl;	/* offset 0x598 */
362 	unsigned int resv35;
363 	unsigned int uart5clkctrl;	/* offset 0x5A0 */
364 	unsigned int resv36[5];
365 	unsigned int usbphyocp2scp0clkctrl;	/* offset 0x5B8 */
366 	unsigned int resv361;
367 	unsigned int usbphyocp2scp1clkctrl;	/* offset 0x5C0 */
368 	unsigned int resv3611[79];
369 
370 	unsigned int emifclkstctrl;	/* offset 0x700 */
371 	unsigned int resv362[7];
372 	unsigned int emifclkctrl;	/* offset 0x720 */
373 	unsigned int resv37[3];
374 	unsigned int emiffwclkctrl;	/* offset 0x730 */
375 	unsigned int resv371;
376 	unsigned int otfaemifclkctrl;	/* offset 0x738 */
377 	unsigned int resv38[57];
378 	unsigned int lcdclkctrl;	/* offset 0x820 */
379 	unsigned int resv39[183];
380 	unsigned int cpswclkstctrl;	/* offset 0xB00 */
381 	unsigned int resv40[7];
382 	unsigned int cpgmac0clkctrl;	/* offset 0xB20 */
383 };
384 
385 struct cm_device_inst {
386 	unsigned int cm_clkout1_ctrl;
387 	unsigned int cm_dll_ctrl;
388 };
389 
390 struct prm_device_inst {
391 	unsigned int rstctrl;
392 	unsigned int rstst;
393 	unsigned int rsttime;
394 	unsigned int sram_count;
395 	unsigned int ldo_sram_core_set;	/* offset 0x10 */
396 	unsigned int ldo_sram_core_ctr;
397 	unsigned int ldo_sram_mpu_setu;
398 	unsigned int ldo_sram_mpu_ctrl;
399 	unsigned int io_count;		/* offset 0x20 */
400 	unsigned int io_pmctrl;
401 	unsigned int vc_val_bypass;
402 	unsigned int resv1;
403 	unsigned int emif_ctrl;		/* offset 0x30 */
404 };
405 
406 struct cm_dpll {
407 	unsigned int resv1;
408 	unsigned int clktimer2clk;	/* offset 0x04 */
409 	unsigned int resv2[11];
410 	unsigned int clkselmacclk;	/* offset 0x34 */
411 };
412 #endif /* CONFIG_AM43XX */
413 
414 /* Control Module RTC registers */
415 struct cm_rtc {
416 	unsigned int rtcclkctrl;	/* offset 0x0 */
417 	unsigned int clkstctrl;		/* offset 0x4 */
418 };
419 
420 /* Timer 32 bit registers */
421 struct gptimer {
422 	unsigned int tidr;		/* offset 0x00 */
423 	unsigned char res1[12];
424 	unsigned int tiocp_cfg;		/* offset 0x10 */
425 	unsigned char res2[12];
426 	unsigned int tier;		/* offset 0x20 */
427 	unsigned int tistatr;		/* offset 0x24 */
428 	unsigned int tistat;		/* offset 0x28 */
429 	unsigned int tisr;		/* offset 0x2c */
430 	unsigned int tcicr;		/* offset 0x30 */
431 	unsigned int twer;		/* offset 0x34 */
432 	unsigned int tclr;		/* offset 0x38 */
433 	unsigned int tcrr;		/* offset 0x3c */
434 	unsigned int tldr;		/* offset 0x40 */
435 	unsigned int ttgr;		/* offset 0x44 */
436 	unsigned int twpc;		/* offset 0x48 */
437 	unsigned int tmar;		/* offset 0x4c */
438 	unsigned int tcar1;		/* offset 0x50 */
439 	unsigned int tscir;		/* offset 0x54 */
440 	unsigned int tcar2;		/* offset 0x58 */
441 };
442 
443 /* UART Registers */
444 struct uart_sys {
445 	unsigned int resv1[21];
446 	unsigned int uartsyscfg;	/* offset 0x54 */
447 	unsigned int uartsyssts;	/* offset 0x58 */
448 };
449 
450 /* VTP Registers */
451 struct vtp_reg {
452 	unsigned int vtp0ctrlreg;
453 };
454 
455 /* Control Status Register */
456 struct ctrl_stat {
457 	unsigned int resv1[16];
458 	unsigned int statusreg;		/* ofset 0x40 */
459 	unsigned int resv2[51];
460 	unsigned int secure_emif_sdram_config;	/* offset 0x0110 */
461 	unsigned int resv3[319];
462 	unsigned int dev_attr;
463 };
464 
465 /* AM33XX GPIO registers */
466 #define OMAP_GPIO_REVISION		0x0000
467 #define OMAP_GPIO_SYSCONFIG		0x0010
468 #define OMAP_GPIO_SYSSTATUS		0x0114
469 #define OMAP_GPIO_IRQSTATUS1		0x002c
470 #define OMAP_GPIO_IRQSTATUS2		0x0030
471 #define OMAP_GPIO_IRQSTATUS_SET_0	0x0034
472 #define OMAP_GPIO_IRQSTATUS_SET_1	0x0038
473 #define OMAP_GPIO_CTRL			0x0130
474 #define OMAP_GPIO_OE			0x0134
475 #define OMAP_GPIO_DATAIN		0x0138
476 #define OMAP_GPIO_DATAOUT		0x013c
477 #define OMAP_GPIO_LEVELDETECT0		0x0140
478 #define OMAP_GPIO_LEVELDETECT1		0x0144
479 #define OMAP_GPIO_RISINGDETECT		0x0148
480 #define OMAP_GPIO_FALLINGDETECT		0x014c
481 #define OMAP_GPIO_DEBOUNCE_EN		0x0150
482 #define OMAP_GPIO_DEBOUNCE_VAL		0x0154
483 #define OMAP_GPIO_CLEARDATAOUT		0x0190
484 #define OMAP_GPIO_SETDATAOUT		0x0194
485 
486 /* Control Device Register */
487 
488  /* Control Device Register */
489 #define MREQPRIO_0_SAB_INIT1_MASK	0xFFFFFF8F
490 #define MREQPRIO_0_SAB_INIT0_MASK	0xFFFFFFF8
491 #define MREQPRIO_1_DSS_MASK		0xFFFFFF8F
492 
493 struct ctrl_dev {
494 	unsigned int deviceid;		/* offset 0x00 */
495 	unsigned int resv1[7];
496 	unsigned int usb_ctrl0;		/* offset 0x20 */
497 	unsigned int resv2;
498 	unsigned int usb_ctrl1;		/* offset 0x28 */
499 	unsigned int resv3;
500 	unsigned int macid0l;		/* offset 0x30 */
501 	unsigned int macid0h;		/* offset 0x34 */
502 	unsigned int macid1l;		/* offset 0x38 */
503 	unsigned int macid1h;		/* offset 0x3c */
504 	unsigned int resv4[4];
505 	unsigned int miisel;		/* offset 0x50 */
506 	unsigned int resv5[7];
507 	unsigned int mreqprio_0;	/* offset 0x70 */
508 	unsigned int mreqprio_1;	/* offset 0x74 */
509 	unsigned int resv6[97];
510 	unsigned int efuse_sma;		/* offset 0x1FC */
511 };
512 
513 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
514 #define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
515 #define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
516 #define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
517 
518 struct l3f_cfg_bwlimiter {
519 	u32 padding0[2];
520 	u32 modena_init0_bw_fractional;
521 	u32 modena_init0_bw_integer;
522 	u32 modena_init0_watermark_0;
523 };
524 
525 /* gmii_sel register defines */
526 #define GMII1_SEL_MII		0x0
527 #define GMII1_SEL_RMII		0x1
528 #define GMII1_SEL_RGMII		0x2
529 #define GMII2_SEL_MII		0x0
530 #define GMII2_SEL_RMII		0x4
531 #define GMII2_SEL_RGMII		0x8
532 #define RGMII1_IDMODE		BIT(4)
533 #define RGMII2_IDMODE		BIT(5)
534 #define RMII1_IO_CLK_EN		BIT(6)
535 #define RMII2_IO_CLK_EN		BIT(7)
536 
537 #define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
538 #define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
539 #define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
540 #define RGMII_INT_DELAY		(RGMII1_IDMODE | RGMII2_IDMODE)
541 #define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
542 
543 /* PWMSS */
544 struct pwmss_regs {
545 	unsigned int idver;
546 	unsigned int sysconfig;
547 	unsigned int clkconfig;
548 	unsigned int clkstatus;
549 };
550 #define ECAP_CLK_EN		BIT(0)
551 #define ECAP_CLK_STOP_REQ	BIT(1)
552 #define EPWM_CLK_EN		BIT(8)
553 #define EPWM_CLK_STOP_REQ	BIT(9)
554 
555 struct pwmss_ecap_regs {
556 	unsigned int tsctr;
557 	unsigned int ctrphs;
558 	unsigned int cap1;
559 	unsigned int cap2;
560 	unsigned int cap3;
561 	unsigned int cap4;
562 	unsigned int resv1[4];
563 	unsigned short ecctl1;
564 	unsigned short ecctl2;
565 };
566 
567 struct pwmss_epwm_regs {
568 	unsigned short tbctl;
569 	unsigned short tbsts;
570 	unsigned short tbphshr;
571 	unsigned short tbphs;
572 	unsigned short tbcnt;
573 	unsigned short tbprd;
574 	unsigned short res1;
575 	unsigned short cmpctl;
576 	unsigned short cmpahr;
577 	unsigned short cmpa;
578 	unsigned short cmpb;
579 	unsigned short aqctla;
580 	unsigned short aqctlb;
581 	unsigned short aqsfrc;
582 	unsigned short aqcsfrc;
583 	unsigned short dbctl;
584 	unsigned short dbred;
585 	unsigned short dbfed;
586 	unsigned short tzsel;
587 	unsigned short tzctl;
588 	unsigned short tzflg;
589 	unsigned short tzclr;
590 	unsigned short tzfrc;
591 	unsigned short etsel;
592 	unsigned short etps;
593 	unsigned short etflg;
594 	unsigned short etclr;
595 	unsigned short etfrc;
596 	unsigned short pcctl;
597 	unsigned int res2[66];
598 	unsigned short hrcnfg;
599 };
600 
601 /* Capture Control register 2 */
602 #define ECTRL2_SYNCOSEL_MASK	(0x03 << 6)
603 #define ECTRL2_MDSL_ECAP	BIT(9)
604 #define ECTRL2_CTRSTP_FREERUN	BIT(4)
605 #define ECTRL2_PLSL_LOW		BIT(10)
606 #define ECTRL2_SYNC_EN		BIT(5)
607 
608 #endif /* __ASSEMBLY__ */
609 #endif /* __KERNEL_STRICT_NAMES */
610 
611 #endif /* _AM33XX_CPU_H */
612