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Searched refs:tc_compatible_htile (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
Dr600_texture.c229 bool tc_compatible_htile) in r600_init_surface() argument
251 if (tc_compatible_htile && in r600_init_surface()
559 rtex->tc_compatible_htile = new_tex->tc_compatible_htile; in r600_reallocate_texture_inplace()
1034 if (sscreen->info.chip_class <= VI && !rtex->tc_compatible_htile) in r600_texture_allocate_htile()
1143 rtex->tc_compatible_htile); in si_print_texture_info()
1220 rtex->tc_compatible_htile = rtex->surface.htile_size != 0 && in r600_texture_create_object()
1227 if (rtex->tc_compatible_htile) { in r600_texture_create_object()
1321 if (sscreen->info.chip_class >= GFX9 || rtex->tc_compatible_htile) in r600_texture_create_object()
1438 bool tc_compatible_htile = in si_texture_create() local
1451 tc_compatible_htile); in si_texture_create()
Dr600_pipe_common.h233 bool tc_compatible_htile:1; member
/external/mesa3d/src/amd/vulkan/
Dradv_image.c271 } else if(!is_storage_image && image->tc_compatible_htile && in si_set_mutable_tex_desc_fields()
423 image->tc_compatible_htile) { in si_make_texture_descriptor()
947 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE; in radv_image_create()
1136 if (image->surface.htile_size && image->tc_compatible_htile) in radv_layout_has_htile()
1149 if (image->surface.htile_size && image->tc_compatible_htile) in radv_layout_is_htile_compressed()
Dradv_meta_copy.c93 !(image->surface.htile_size && image->tc_compatible_htile)) in blit_surf_for_image_level_layer()
Dradv_device.c3360 if (iview->image->tc_compatible_htile) { in radv_initialise_ds_surface()
3391 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile); in radv_initialise_ds_surface()
3436 !iview->image->tc_compatible_htile) in radv_initialise_ds_surface()
3445 if (iview->image->tc_compatible_htile) { in radv_initialise_ds_surface()
Dradv_private.h1381 bool tc_compatible_htile; member
Dradv_meta_clear.c556 if (iview->image->tc_compatible_htile && in depth_view_can_fast_clear()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.h923 assert(!tex->tc_compatible_htile || tex->htile_offset); in vi_tc_compat_htile_enabled()
924 return tex->tc_compatible_htile && level == 0; in vi_tc_compat_htile_enabled()
Dsi_clear.c558 (!zstex->tc_compatible_htile || in si_clear()
575 (!zstex->tc_compatible_htile || stencil == 0)) { in si_clear()
Dsi_state.c2547 if (rtex->tc_compatible_htile) { in si_init_depth_surface()
2589 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile); in si_init_depth_surface()
2639 } else if (!rtex->tc_compatible_htile) { in si_init_depth_surface()
2651 if (rtex->tc_compatible_htile) { in si_init_depth_surface()
3658 tex->tc_compatible_htile) in si_make_texture_descriptor()