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Searched refs:tcc_cache_line_size (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.h842 unsigned alignment, tcc_cache_line_size; in si_optimal_tcc_alignment() local
850 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size; in si_optimal_tcc_alignment()
851 return MIN2(alignment, tcc_cache_line_size); in si_optimal_tcc_alignment()
Dsi_pipe.c364 sctx->screen->info.tcc_cache_line_size); in si_create_context()
Dsi_compute.c627 sctx->screen->info.tcc_cache_line_size, in si_upload_compute_input()
Dsi_state_draw.c1364 sctx->screen->info.tcc_cache_line_size, in si_draw_vbo()
/external/mesa3d/src/amd/common/
Dac_gpu_info.h77 uint32_t tcc_cache_line_size; member
Dac_gpu_info.c297 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */ in ac_query_gpu_info()
408 printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size); in ac_print_gpu_info()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_pipe_common.c185 rctx->screen->info.tcc_cache_line_size, in r600_draw_rectangle()
1371 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size); in r600_common_screen_init()
Dr600_buffer_common.c427 rctx->screen->info.tcc_cache_line_size, in r600_buffer_transfer_map()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_buffer_common.c436 rctx->screen->info.tcc_cache_line_size, in r600_buffer_transfer_map()
/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c527 ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ in do_winsys_init()