| /external/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| D | lpddr3_stock.c | 27 u8 tcke = 3; in mctl_set_timing_params() local
66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| D | ddr3_1333.c | 27 u8 tcke = 3; in mctl_set_timing_params() local
70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| D | ddr2_v3s.c | 27 u8 tcke = 3; in mctl_set_timing_params() local
67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | ddr.c | 998 u8 tcke, tcksrx, tcksre, trrd; in mx6_lpddr2_cfg() local
1042 tcke = 3; in mx6_lpddr2_cfg()
1080 debug("tcke=%d\n", tcke); in mx6_lpddr2_cfg()
1199 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_lpddr2_cfg()
1228 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; in mx6_ddr3_cfg() local
1302 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1313 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1; in mx6_ddr3_cfg()
1347 debug("tcke=%d\n", tcke); in mx6_ddr3_cfg()
1500 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_ddr3_cfg()
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| /external/u-boot/arch/arm/include/asm/arch-omap3/ |
| D | mem.h | 82 #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ argument
84 ACTIM_CTRLB_TCKE(tcke) | \
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| /external/u-boot/arch/arm/include/asm/arch-vf610/ |
| D | ddrmc-vf610.h | 32 u8 tcke; member
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| /external/u-boot/arch/arm/include/asm/arch-tegra20/ |
| D | emc.h | 50 u32 tcke; /* 0x94: EMC_TCKE */ member
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | sdram.h | 71 u32 tcke; member
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| D | sdram_rk3036.h | 68 u32 tcke; member
265 u32 tcke; member
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| D | sdram_rk322x.h | 104 u32 tcke; member
230 u32 tcke; member
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| D | ddr_rk3368.h | 72 u32 tcke; member
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| D | ddr_rk3288.h | 67 u32 tcke; member
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun8i_a33.c | 111 u8 tcke = 3; in auto_set_timing_para() local
148 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| D | dram_sun8i_a83t.c | 111 u8 tcke = 3; in auto_set_timing_para() local
180 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| D | dram_sun6i.c | 230 writel(MCTL_TCKE, &mctl_ctl->tcke); in mctl_channel_init()
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| /external/u-boot/board/phytec/pcm052/ |
| D | pcm052.c | 228 .tcke = 3, in dram_init()
283 .tcke = 3, in dram_init()
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| /external/u-boot/arch/arm/mach-imx/ |
| D | ddrmc-vf610.c | 135 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); in ddrmc_ctrl_init_ddr3()
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| /external/u-boot/board/freescale/vf610twr/ |
| D | vf610twr.c | 106 .tcke = 3, in dram_init()
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| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | dram_sun6i.h | 95 u32 tcke; /* 0x12c */ member
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| /external/u-boot/drivers/ram/rockchip/ |
| D | dmc-rk3368.c | 513 pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq)); in pctl_calc_timings()
518 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ in pctl_calc_timings()
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3288-dmc.txt | 81 tcke
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| /external/u-boot/board/toradex/colibri_vf/ |
| D | colibri_vf.c | 125 .tcke = 3, in dram_init()
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