| /external/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| D | lpddr3_stock.c | 34 u8 tcwl = 3; /* CWL 6 */ in mctl_set_timing_params() local
43 u8 twtp = tcwl + 4 + twr + 1; in mctl_set_timing_params()
44 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_params()
45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1; in mctl_set_timing_params()
58 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| D | ddr3_1333.c | 34 u8 tcwl = 4; /* CWL 8 */ in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
62 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| D | ddr2_v3s.c | 34 u8 tcwl = 3; /* CWL 6 */ in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
59 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun8i_a83t.c | 117 u8 tcwl = 4; /* CWL 8 */ in auto_set_timing_para() local
126 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in auto_set_timing_para()
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
159 tcwl = 3; /* CWL 8 */ in auto_set_timing_para()
165 twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */ in auto_set_timing_para()
166 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
167 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
174 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
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| D | dram_sun8i_a33.c | 117 u8 tcwl = 4; /* CWL 8 */ in auto_set_timing_para() local
126 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in auto_set_timing_para()
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
142 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
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| D | dram_sun6i.c | 214 writel(MCTL_TCWL, &mctl_ctl->tcwl); in mctl_channel_init()
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| /external/u-boot/drivers/ram/rockchip/ |
| D | dmc-rk3368.c | 155 u32 tcl, u32 tal, u32 tcwl) in ddrphy_config() argument
165 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl); in ddrphy_config()
241 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl); in memory_init()
473 pctl_timing->tcwl = 10; in pctl_calc_timings()
476 pctl_timing->tcwl = 6; in pctl_calc_timings()
479 pctl_timing->tcwl = 7; in pctl_calc_timings()
482 pctl_timing->tcwl = 8; in pctl_calc_timings()
493 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; in pctl_calc_timings()
560 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
832 params->pctl_timing.tcwl); in setup_sdram()
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| D | sdram_rk322x.c | 430 writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
444 writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
497 writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]); in phy_cfg()
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| D | sdram_rk3288.c | 252 writel(sdram_params->pctl_timing.tcwl, in pctl_cfg()
273 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
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| D | sdram_rk3188.c | 241 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | ddr.c | 1229 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; in mx6_ddr3_cfg() local
1249 tcwl = 4; in mx6_ddr3_cfg()
1256 tcwl = 3; in mx6_ddr3_cfg()
1270 todtlon = tcwl; in mx6_ddr3_cfg()
1271 taxpd = tcwl; in mx6_ddr3_cfg()
1272 tanpd = tcwl; in mx6_ddr3_cfg()
1367 debug("tcwl=%d\n", tcwl); in mx6_ddr3_cfg()
1436 (twr << 9) | (tmrd << 5) | tcwl; in mx6_ddr3_cfg()
1476 ((tcwl - 3) & 3) << 3; in mx6_ddr3_cfg()
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | sdram.h | 55 u32 tcwl; member
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| D | sdram_rk3036.h | 52 u32 tcwl; member
249 u32 tcwl; member
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| D | sdram_rk322x.h | 88 u32 tcwl; member
214 u32 tcwl; member
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| D | ddr_rk3368.h | 56 u32 tcwl; member
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| D | ddr_rk3288.h | 51 u32 tcwl; member
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| /external/u-boot/board/freescale/mx6qarm2/ |
| D | imximage_mx6dl.cfg | 284 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
296 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
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| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | dram_sun6i.h | 79 u32 tcwl; /* 0xec */ member
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3288-dmc.txt | 65 tcwl
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| /external/u-boot/arch/arm/mach-rockchip/rk3036/ |
| D | sdram_rk3036.c | 612 reg = readl(&pctl->tcwl); in pctl_cfg()
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