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Searched refs:teqi (Results 1 – 25 of 91) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll26 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
39 ; ALL: teqi $zero, 1
60 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
73 ; ALL: teqi $zero, 1
90 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
101 ; ALL: teqi $zero, 1
118 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
131 ; ALL: teqi $zero, 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll26 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
39 ; ALL: teqi $zero, 1
60 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
73 ; ALL: teqi $zero, 1
90 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
101 ; ALL: teqi $zero, 1
118 …call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7…
131 ; ALL: teqi $zero, 1
/external/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs.ll58 ; ALL: teqi $zero, 1
92 ; ALL: teqi $zero, 2
120 call void asm sideeffect "teqi $$zero, 1", ""()
125 call void asm sideeffect "teqi $$zero, 2", ""()
176 ; ALL: teqi $zero, 1
210 ; ALL: teqi $zero, 2
238 call void asm sideeffect "teqi $$zero, 1", ""()
243 call void asm sideeffect "teqi $$zero, 2", ""()
294 ; ALL: teqi $zero, 1
331 ; ALL: teqi $zero, 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs.ll58 ; ALL: teqi $zero, 1
92 ; ALL: teqi $zero, 2
120 call void asm sideeffect "teqi $$zero, 1", ""()
125 call void asm sideeffect "teqi $$zero, 2", ""()
176 ; ALL: teqi $zero, 1
210 ; ALL: teqi $zero, 2
238 call void asm sideeffect "teqi $$zero, 1", ""()
243 call void asm sideeffect "teqi $$zero, 2", ""()
294 ; ALL: teqi $zero, 1
330 ; ALL: teqi $zero, 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmicromips-trap-instructions.s18 # CHECK-EL: teqi $9, 17767 # encoding: [0xc9,0x41,0x67,0x45]
33 # CHECK-EB: teqi $9, 17767 # encoding: [0x41,0xc9,0x45,0x67]
45 teqi $9, 17767
Dmips-control-instructions.s24 # CHECK32: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
59 # CHECK64: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
93 teqi $3,1
/external/llvm/test/MC/Mips/
Dmicromips-trap-instructions.s18 # CHECK-EL: teqi $9, 17767 # encoding: [0xc9,0x41,0x67,0x45]
33 # CHECK-EB: teqi $9, 17767 # encoding: [0x41,0xc9,0x45,0x67]
45 teqi $9, 17767
Dmips-control-instructions.s20 # CHECK32: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
51 # CHECK64: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
85 teqi $3,1
/external/capstone/suite/MC/Mips/
Dmicromips-trap-instructions.s.cs8 0xc9,0x41,0x67,0x45 = teqi $9, 17767
Dmicromips-trap-instructions-EB.s.cs8 0x41,0xc9,0x45,0x67 = teqi $9, 17767
Dmips-control-instructions-64.s.cs18 0x04,0x6c,0x00,0x01 = teqi $3, 1
Dmips-control-instructions.s.cs18 0x04,0x6c,0x00,0x01 = teqi $3, 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips3.s24 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips2.s34 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips64.s45 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips3.s24 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips2.s34 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips64.s45 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips2.s31 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips2.s31 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/
Dvalid.s220 … teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips2.s30 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/
Dinvalid-mips2.s30 …teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/
Dvalid.s283 … teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32/
Dvalid.s282 … teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]

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