| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 505 uint32_t tiling_flags = 0; in radv_amdgpu_winsys_bo_set_metadata() local
508 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in radv_amdgpu_winsys_bo_set_metadata()
511 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
513 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
515 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */ in radv_amdgpu_winsys_bo_set_metadata()
517 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config); in radv_amdgpu_winsys_bo_set_metadata()
518 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw)); in radv_amdgpu_winsys_bo_set_metadata()
519 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh)); in radv_amdgpu_winsys_bo_set_metadata()
521 tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->u.legacy.tile_split)); in radv_amdgpu_winsys_bo_set_metadata()
522 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea)); in radv_amdgpu_winsys_bo_set_metadata()
[all …]
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_bo.c | 1081 uint64_t tiling_flags; in amdgpu_buffer_get_metadata() local
1090 tiling_flags = info.metadata.tiling_info; in amdgpu_buffer_get_metadata()
1093 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in amdgpu_buffer_get_metadata()
1098 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */ in amdgpu_buffer_get_metadata()
1100 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */ in amdgpu_buffer_get_metadata()
1103 md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in amdgpu_buffer_get_metadata()
1104 md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_buffer_get_metadata()
1105 md->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in amdgpu_buffer_get_metadata()
1106 md->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); in amdgpu_buffer_get_metadata()
1107 md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_buffer_get_metadata()
[all …]
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| /external/libdrm/radeon/ |
| D | radeon_bo.c | 98 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling() argument
101 return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch); in radeon_bo_set_tiling()
106 uint32_t *tiling_flags, uint32_t *pitch) in radeon_bo_get_tiling() argument
109 return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch); in radeon_bo_get_tiling()
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| D | radeon_bo_gem.c | 232 static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags, in bo_set_tiling() argument
239 args.tiling_flags = tiling_flags; in bo_set_tiling()
249 static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags, in bo_get_tiling() argument
265 *tiling_flags = args.tiling_flags; in bo_get_tiling()
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| D | radeon_bo.h | 68 int radeon_bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch);
69 int radeon_bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch);
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| D | radeon_bo_int.h | 37 int (*bo_set_tiling)(struct radeon_bo_int *bo, uint32_t tiling_flags,
39 int (*bo_get_tiling)(struct radeon_bo_int *bo, uint32_t *tiling_flags,
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_bo.c | 855 if (args.tiling_flags & RADEON_TILING_MICRO) in radeon_bo_get_metadata()
857 else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE) in radeon_bo_get_metadata()
860 if (args.tiling_flags & RADEON_TILING_MACRO) in radeon_bo_get_metadata()
863 …md->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_… in radeon_bo_get_metadata()
864 …md->u.legacy.bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_… in radeon_bo_get_metadata()
865 …md->u.legacy.tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING… in radeon_bo_get_metadata()
866 …md->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TIL… in radeon_bo_get_metadata()
868 …md->u.legacy.scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANO… in radeon_bo_get_metadata()
884 args.tiling_flags |= RADEON_TILING_MICRO; in radeon_bo_set_metadata()
886 args.tiling_flags |= RADEON_TILING_MICRO_SQUARE; in radeon_bo_set_metadata()
[all …]
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| /external/mesa3d/src/intel/isl/tests/ |
| D | isl_surf_get_image_offset_test.c | 145 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0()
193 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0()
254 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_common_context.c | 512 uint32_t tiling_flags = 0, pitch = 0; in radeon_update_renderbuffers() local
528 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch); in radeon_update_renderbuffers()
537 if (tiling_flags & RADEON_TILING_MACRO) in radeon_update_renderbuffers()
539 if (tiling_flags & RADEON_TILING_MICRO) in radeon_update_renderbuffers()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_common_context.c | 512 uint32_t tiling_flags = 0, pitch = 0; in radeon_update_renderbuffers() local
528 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch); in radeon_update_renderbuffers()
537 if (tiling_flags & RADEON_TILING_MACRO) in radeon_update_renderbuffers()
539 if (tiling_flags & RADEON_TILING_MICRO) in radeon_update_renderbuffers()
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| /external/mesa3d/src/intel/isl/ |
| D | isl.c | 326 isl_tiling_flags_t tiling_flags = info->tiling_flags; in isl_surf_choose_tiling() local
331 assert(tiling_flags == ISL_TILING_HIZ_BIT); in isl_surf_choose_tiling()
339 assert(tiling_flags == ISL_TILING_CCS_BIT); in isl_surf_choose_tiling()
345 isl_gen6_filter_tiling(dev, info, &tiling_flags); in isl_surf_choose_tiling()
347 isl_gen4_filter_tiling(dev, info, &tiling_flags); in isl_surf_choose_tiling()
352 if (tiling_flags & (1u << (__tiling))) { \ in isl_surf_choose_tiling()
1629 .tiling_flags = ISL_TILING_HIZ_BIT); in isl_surf_get_hiz_surf()
1675 .tiling_flags = ISL_TILING_Y0_BIT); in isl_surf_get_mcs_surf()
1762 .tiling_flags = ISL_TILING_CCS_BIT); in isl_surf_get_ccs_surf()
2218 .tiling_flags = (1 << surf->tiling)); in isl_surf_get_image_surf()
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| D | isl.h | 1115 isl_tiling_flags_t tiling_flags; member
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| /external/mesa3d/src/intel/vulkan/ |
| D | anv_image.c | 285 isl_tiling_flags_t tiling_flags, in make_surface() argument
320 tiling_flags = ISL_TILING_LINEAR_BIT; in make_surface()
336 .tiling_flags = tiling_flags); in make_surface()
351 assert(tiling_flags == ISL_TILING_LINEAR_BIT); in make_surface()
365 .tiling_flags = ISL_TILING_ANY_MASK); in make_surface()
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| D | anv_blorp.c | 172 .tiling_flags = ISL_TILING_LINEAR_BIT); in get_blorp_surf_for_anv_buffer()
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| /external/kernel-headers/original/uapi/drm/ |
| D | radeon_drm.h | 858 __u32 tiling_flags; member
864 __u32 tiling_flags; member
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| /external/libdrm/include/drm/ |
| D | radeon_drm.h | 859 __u32 tiling_flags; member
865 __u32 tiling_flags; member
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_mipmap_tree.c | 554 unsigned num_samples, isl_tiling_flags_t tiling_flags, in make_surface() argument
592 .tiling_flags = tiling_flags, in make_surface()
608 init_info.tiling_flags = 1u << ISL_TILING_LINEAR; in make_surface()
612 init_info.tiling_flags = 1u << ISL_TILING_X; in make_surface()
740 isl_tiling_flags_t tiling_flags = (flags & MIPTREE_CREATE_LINEAR) ? in miptree_create() local
745 tiling_flags &= ~ISL_TILING_Y0_BIT; in miptree_create()
751 num_samples, tiling_flags, in miptree_create()
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| D | intel_screen.c | 714 .tiling_flags = (1 << mod_info->tiling)); in intel_create_image_common()
1101 .tiling_flags = (1 << mod_info->tiling)); in intel_create_image_from_fds_common()
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| /external/mesa3d/src/intel/blorp/ |
| D | blorp_blit.c | 2585 .tiling_flags = ISL_TILING_LINEAR_BIT); in do_buffer_copy()
|