/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_bufmgr.c | 124 static int bo_set_tiling_internal(struct brw_bo *bo, uint32_t tiling_mode, 270 uint32_t tiling_mode, in bo_alloc_internal() argument 346 if (bo_set_tiling_internal(bo, tiling_mode, stride)) { in bo_alloc_internal() 386 bo->tiling_mode = I915_TILING_NONE; in bo_alloc_internal() 390 if (bo_set_tiling_internal(bo, tiling_mode, stride)) in bo_alloc_internal() 436 uint64_t size, uint32_t tiling_mode, uint32_t pitch, in brw_bo_alloc_tiled() argument 439 return bo_alloc_internal(bufmgr, name, size, flags, tiling_mode, pitch, 0); in brw_bo_alloc_tiled() 549 bo->tiling_mode = get_tiling.tiling_mode; in brw_bo_gem_create_from_name() 931 if (bo->tiling_mode != I915_TILING_NONE && !(flags & MAP_RAW)) in brw_bo_map() 1069 bo_set_tiling_internal(struct brw_bo *bo, uint32_t tiling_mode, in bo_set_tiling_internal() argument [all …]
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D | brw_bufmgr.h | 138 uint32_t tiling_mode; member 197 uint32_t tiling_mode, 219 uint32_t tiling_mode, 284 int brw_bo_get_tiling(struct brw_bo *bo, uint32_t *tiling_mode, 341 uint32_t tiling_mode,
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D | intel_screen.c | 485 image->modifier = tiling_to_modifier(image->bo->tiling_mode); in intel_create_image_from_name() 1074 image->modifier = tiling_to_modifier(image->bo->tiling_mode); in intel_create_image_from_fds_common()
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/external/libdrm/intel/ |
D | intel_bufmgr.c | 65 uint32_t tiling_mode, in drm_intel_bo_alloc_userptr() argument 71 return bufmgr->bo_alloc_userptr(bufmgr, name, addr, tiling_mode, in drm_intel_bo_alloc_userptr() 78 int x, int y, int cpp, uint32_t *tiling_mode, in drm_intel_bo_alloc_tiled() argument 82 tiling_mode, pitch, flags); in drm_intel_bo_alloc_tiled() 239 drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, in drm_intel_bo_set_tiling() argument 243 return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride); in drm_intel_bo_set_tiling() 245 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_set_tiling() 250 drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, in drm_intel_bo_get_tiling() argument 254 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); in drm_intel_bo_get_tiling() 256 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_get_tiling()
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D | intel_bufmgr_gem.c | 191 uint32_t tiling_mode; member 293 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 298 uint32_t tiling_mode, 315 uint32_t *tiling_mode) in drm_intel_gem_bo_tile_size() argument 320 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_size() 337 *tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_tile_size() 358 unsigned long pitch, uint32_t *tiling_mode) in drm_intel_gem_bo_tile_pitch() argument 366 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_pitch() 369 if (*tiling_mode == I915_TILING_X in drm_intel_gem_bo_tile_pitch() 371 && *tiling_mode == I915_TILING_Y)) in drm_intel_gem_bo_tile_pitch() [all …]
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D | intel_bufmgr_priv.h | 72 uint32_t tiling_mode, uint32_t stride, 94 uint32_t *tiling_mode, 230 int (*bo_set_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode, 240 int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
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D | intel_bufmgr.h | 122 void *addr, uint32_t tiling_mode, 128 uint32_t *tiling_mode, 160 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 162 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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D | intel_bufmgr_fake.c | 841 uint32_t *tiling_mode, in drm_intel_fake_bo_alloc_tiled() argument 848 *tiling_mode = I915_TILING_NONE; in drm_intel_fake_bo_alloc_tiled()
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/external/libxcam/xcore/ |
D | drm_bo_buffer.cpp | 55 uint32_t tiling_mode, swizzle_mode; in map() local 57 drm_intel_bo_get_tiling (_bo, &tiling_mode, &swizzle_mode); in map() 59 if (tiling_mode != OCL_TILING_NONE) { in map() 78 uint32_t tiling_mode, swizzle_mode; in unmap() local 80 drm_intel_bo_get_tiling (_bo, &tiling_mode, &swizzle_mode); in unmap() 82 if (tiling_mode != OCL_TILING_NONE) { in unmap()
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/external/mesa3d/src/gallium/winsys/i915/drm/ |
D | i915_drm_buffer.c | 63 uint32_t tiling_mode = *tiling; in i915_drm_buffer_create_tiled() local 75 &tiling_mode, &pitch, 0); in i915_drm_buffer_create_tiled() 81 *tiling = tiling_mode; in i915_drm_buffer_create_tiled()
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/external/mesa3d/src/intel/vulkan/ |
D | anv_gem.c | 208 return get_tiling.tiling_mode; in anv_gem_get_tiling() 223 .tiling_mode = tiling, in anv_gem_set_tiling() 273 .tiling_mode = tiling, in anv_gem_get_bit6_swizzle()
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/external/libdrm/libkms/ |
D | intel.c | 123 tile.tiling_mode = I915_TILING_X; in intel_bo_create()
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/external/minigbm/ |
D | i915.c | 389 gem_set_tiling.tiling_mode = bo->tiling; in i915_bo_create_for_modifier() 459 bo->tiling = gem_get_tiling.tiling_mode; in i915_bo_import()
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/external/mesa3d/include/drm-uapi/ |
D | i915_drm.h | 1159 __u32 tiling_mode; member 1182 __u32 tiling_mode; member
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/external/libdrm/include/drm/ |
D | i915_drm.h | 1201 __u32 tiling_mode; member 1224 __u32 tiling_mode; member
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/external/kernel-headers/original/uapi/drm/ |
D | i915_drm.h | 1231 __u32 tiling_mode; member 1254 __u32 tiling_mode; member
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