Searched refs:tim1 (Results 1 – 1 of 1) sorted by relevance
686 u32 tim1 = 0, val = 0; in get_sdram_tim_1_reg() local688 tim1 |= val << EMIF_REG_T_WTR_SHIFT; in get_sdram_tim_1_reg()696 tim1 |= val << EMIF_REG_T_RRD_SHIFT; in get_sdram_tim_1_reg()699 tim1 |= val << EMIF_REG_T_RC_SHIFT; in get_sdram_tim_1_reg()702 tim1 |= val << EMIF_REG_T_RAS_SHIFT; in get_sdram_tim_1_reg()705 tim1 |= val << EMIF_REG_T_WR_SHIFT; in get_sdram_tim_1_reg()708 tim1 |= val << EMIF_REG_T_RCD_SHIFT; in get_sdram_tim_1_reg()711 tim1 |= val << EMIF_REG_T_RP_SHIFT; in get_sdram_tim_1_reg()713 return tim1; in get_sdram_tim_1_reg()