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Searched refs:timing_cfg_8 (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/board/freescale/ls1043ardb/
Dddr.h91 .timing_cfg_8 = 0x02115600,
/external/u-boot/include/
Dfsl_immap.h85 u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ member
Dfsl_ddr_sdram.h281 unsigned int timing_cfg_8; member
/external/u-boot/drivers/ddr/fsl/
Dfsl_ddr_gen4.c163 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); in fsl_ddr_set_memctl_regs()
Dctrl_regs.c2085 ddr->timing_cfg_8 = (0 in set_timing_cfg_8()
2095 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); in set_timing_cfg_8()
Dinteractive.c663 CFG_REGS(timing_cfg_8), in print_fsl_memctl_config_regs()
754 CFG_REGS(timing_cfg_8), in fsl_ddr_regs_edit()