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Searched refs:timing_cfg_9 (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/board/freescale/ls1043ardb/
Dddr.h92 .timing_cfg_9 = 0,
/external/u-boot/include/
Dfsl_immap.h86 u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ member
Dfsl_ddr_sdram.h282 unsigned int timing_cfg_9; member
/external/u-boot/drivers/ddr/fsl/
Dfsl_ddr_gen4.c164 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); in fsl_ddr_set_memctl_regs()
Dctrl_regs.c2112 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 | in set_timing_cfg_9()
2115 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
Dinteractive.c664 CFG_REGS(timing_cfg_9), in print_fsl_memctl_config_regs()
755 CFG_REGS(timing_cfg_9), in fsl_ddr_regs_edit()