Searched refs:tlb_addr (Results 1 – 9 of 9) sorted by relevance
29 u64 *page_table = (u64 *)gd->arch.tlb_addr; in set_section_dcache()33 u32 *page_table = (u32 *)gd->arch.tlb_addr; in set_section_dcache()56 u64 *page_table = (u64 *)gd->arch.tlb_addr; in mmu_set_region_dcache_behaviour()58 u32 *page_table = (u32 *)gd->arch.tlb_addr; in mmu_set_region_dcache_behaviour()126 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4)); in mmu_setup()127 u64 tpt = gd->arch.tlb_addr + (4096 * i); in mmu_setup()147 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) in mmu_setup()159 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) in mmu_setup()176 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; in mmu_setup()189 : : "r" (gd->arch.tlb_addr) : "memory"); in mmu_setup()
121 pte = (u64*)gd->arch.tlb_addr; in find_pte()150 if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size) in create_table()153 gd->arch.tlb_fillptr - gd->arch.tlb_addr, in create_table()367 if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr) in setup_pgtables()384 u64 tlb_addr = gd->arch.tlb_addr; in setup_all_pgtables() local388 gd->arch.tlb_fillptr = tlb_addr; in setup_all_pgtables()395 (uintptr_t)gd->arch.tlb_addr; in setup_all_pgtables()396 gd->arch.tlb_addr = gd->arch.tlb_fillptr; in setup_all_pgtables()398 gd->arch.tlb_emerg = gd->arch.tlb_addr; in setup_all_pgtables()399 gd->arch.tlb_addr = tlb_addr; in setup_all_pgtables()[all …]
77 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; in early_mmu_setup()78 gd->arch.tlb_fillptr = gd->arch.tlb_addr; in early_mmu_setup()85 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, in early_mmu_setup()147 u64 tlb_addr_save = gd->arch.tlb_addr; in final_mmu_setup()205 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; in final_mmu_setup()211 tlb_addr_save = gd->arch.tlb_addr; in final_mmu_setup()215 gd->arch.tlb_addr = tlb_addr_save; in final_mmu_setup()227 gd->arch.tlb_addr = gd->arch.tlb_fillptr; in final_mmu_setup()228 gd->arch.tlb_emerg = gd->arch.tlb_addr; in final_mmu_setup()230 gd->arch.tlb_addr = tlb_addr_save; in final_mmu_setup()[all …]
101 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1); in board_init_f()102 gd->arch.tlb_allocated = gd->arch.tlb_addr; in board_init_f()
146 u32 *level0_table = (u32 *)gd->arch.tlb_addr; in mmu_setup()147 u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000); in mmu_setup()209 mmu_page_table_flush(gd->arch.tlb_addr, in enable_caches()210 gd->arch.tlb_addr + gd->arch.tlb_size); in enable_caches()
335 gd->arch.tlb_addr = gd->relocaddr; in reserve_mmu()336 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, in reserve_mmu()337 gd->arch.tlb_addr + gd->arch.tlb_size); in reserve_mmu()344 gd->arch.tlb_allocated = gd->arch.tlb_addr; in reserve_mmu()
39 unsigned long tlb_addr; member
113 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; in reserve_mmu()
325 print_num("TLB addr", gd->arch.tlb_addr); in do_bdinfo()