Home
last modified time | relevance | path

Searched refs:tmp26 (Results 1 – 25 of 240) sorted by relevance

12345678910

/external/llvm/test/Transforms/ObjCARC/
Dweak-dce.ll13 %tmp26 = call i8* @objc_loadWeakRetained(i8** %weakBlock) nounwind
25 %tmp26 = call i8* @objc_loadWeakRetained(i8** %weakBlock) nounwind
27 ret i8* %tmp26
38 %tmp26 = call i8* @objc_loadWeakRetained(i8** %weakBlock) nounwind
40 ret i8* %tmp26
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/ObjCARC/
Dweak-dce.ll13 %tmp26 = call i8* @objc_loadWeakRetained(i8** %weakBlock) nounwind
25 %tmp26 = call i8* @objc_loadWeakRetained(i8** %weakBlock) nounwind
27 ret i8* %tmp26
38 %tmp26 = call i8* @objc_loadWeakRetained(i8** %weakBlock) nounwind
40 ret i8* %tmp26
/external/llvm/test/Transforms/InstCombine/
D2006-12-01-BadFPVectorXform.ll4 define <4 x float> @test(<4 x float> %tmp26, <4 x float> %tmp53) {
7 ; CHECK-NEXT: [[TMP64:%.*]] = fadd <4 x float> %tmp26, %tmp53
11 %tmp64 = fadd <4 x float> %tmp26, %tmp53
D2006-12-08-Phi-ICmp-Op-Fold.ll42 %tmp26 = icmp sgt i32 %tmp13, 0 ; <i1> [#uses=1]
43 %tmp26.upgrd.5 = zext i1 %tmp26 to i32 ; <i32> [#uses=1]
47 …%retval.0 = phi i32 [ %tmp14.upgrd.4, %cond_true ], [ %tmp26.upgrd.5, %cond_false ] ; <i32> [#use…
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D2006-12-01-BadFPVectorXform.ll4 define <4 x float> @test(<4 x float> %tmp26, <4 x float> %tmp53) {
7 ; CHECK-NEXT: [[TMP64:%.*]] = fadd <4 x float> %tmp26, %tmp53
11 %tmp64 = fadd <4 x float> %tmp26, %tmp53
D2006-12-08-Phi-ICmp-Op-Fold.ll42 %tmp26 = icmp sgt i32 %tmp13, 0 ; <i1> [#uses=1]
43 %tmp26.upgrd.5 = zext i1 %tmp26 to i32 ; <i32> [#uses=1]
47 …%retval.0 = phi i32 [ %tmp14.upgrd.4, %cond_true ], [ %tmp26.upgrd.5, %cond_false ] ; <i32> [#use…
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ScalarEvolution/
Dtruncate.ll38 %tmp15 = phi i8 [ %arg1, %bb12 ], [ %tmp26, %bb34 ]
55 %tmp26 = add i8 %tmp15, -2
56 %tmp27 = sext i8 %tmp26 to i64
95 %tmp26 = sext i32 %tmp25 to i64
97 %tmp28 = mul i64 %tmp27, %tmp26
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
D2006-12-08-Phi-ICmp-Op-Fold.ll42 %tmp26 = icmp sgt i32 %tmp13, 0 ; <i1> [#uses=1]
43 %tmp26.upgrd.5 = zext i1 %tmp26 to i32 ; <i32> [#uses=1]
47 …%retval.0 = phi i32 [ %tmp14.upgrd.4, %cond_true ], [ %tmp26.upgrd.5, %cond_false ] ; <i32> [#use…
D2006-12-01-BadFPVectorXform.ll4 define <4 x float> @test(<4 x float> %tmp26, <4 x float> %tmp53) {
6 %tmp64 = fadd <4 x float> %tmp26, %tmp53 ; <<4 x float>> [#uses=1]
/external/llvm/test/Transforms/IndVarSimplify/
Dpolynomial-expand.ll13 %tmp26 = phi i32 [ %tmp41, %bb40 ], [ undef, %bb20 ] ; <i32> [#uses=2]
14 %tmp27 = add nsw i32 %tmp26, -1 ; <i32> [#uses=1]
31 %tmp41 = sub i32 %tmp26, %tmp25 ; <i32> [#uses=1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Dpolynomial-expand.ll13 %tmp26 = phi i32 [ %tmp41, %bb40 ], [ undef, %bb20 ] ; <i32> [#uses=2]
14 %tmp27 = add nsw i32 %tmp26, -1 ; <i32> [#uses=1]
31 %tmp41 = sub i32 %tmp26, %tmp25 ; <i32> [#uses=1]
/external/swiftshader/third_party/LLVM/test/Transforms/IndVarSimplify/
Dpolynomial-expand.ll13 %tmp26 = phi i32 [ %tmp41, %bb40 ], [ undef, %bb20 ] ; <i32> [#uses=2]
14 %tmp27 = add nsw i32 %tmp26, -1 ; <i32> [#uses=1]
31 %tmp41 = sub i32 %tmp26, %tmp25 ; <i32> [#uses=1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dspill-cfg-position.ll31 %tmp26 = load i32, i32 addrspace(1)* %tmp25, align 4
46 %tmp41 = mul nsw i32 %tmp28, %tmp26
55 %tmp48 = mul nsw i32 %tmp26, %tmp24
66 %tmp57 = mul nsw i32 %tmp30, %tmp26
Dnot-scalarize-volatile-load.ll12 %tmp26 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 5
13 store i32 %tmp18, i32 addrspace(1)* %tmp26, align 4
Dstore-barrier.ll26 %tmp26 = sext i32 %tmp25 to i64
30 %tmp30 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 %tmp27
34 %tmp35 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 0
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2008-03-10-RegAllocInfLoop.ll11 …%tmp26 = call fastcc i8* @w_addchar( i8* null, i32* %word_length, i32* %max_length, i8 signext %t…
12 store i8* %tmp26, i8** %word, align 4
/external/llvm/test/CodeGen/X86/
D2008-03-10-RegAllocInfLoop.ll11 …%tmp26 = call fastcc i8* @w_addchar( i8* null, i32* %word_length, i32* %max_length, i8 signext %t…
12 store i8* %tmp26, i8** %word, align 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D2008-03-10-RegAllocInfLoop.ll11 …%tmp26 = call fastcc i8* @w_addchar( i8* null, i32* %word_length, i32* %max_length, i8 signext %t…
12 store i8* %tmp26, i8** %word, align 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/
Dpr33706.ll44 %tmp26 = ashr i32 %tmp24, 16
45 store i32 %tmp26, i32* @global, align 4
49 %tmp28 = phi i32 [ %tmp26, %bb22 ], [ %tmp8, %bb7 ]
/external/llvm/test/CodeGen/AMDGPU/
Dstore-barrier.ll26 %tmp26 = sext i32 %tmp25 to i64
30 %tmp30 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 %tmp27
34 %tmp35 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 0
Dsgpr-copy.ll26 %tmp26 = fsub float -0.000000e+00, %tmp21
30 %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ]
47 %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 52)
91 %tmp69 = fmul float %tmp26, %tmp68
168 %tmp26 = bitcast i32 %tmp25 to float
169 %tmp27 = bitcast float %tmp26 to i32
238 %tmp26 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp25, !tbaa !0
240 %tmp26.bc = bitcast <16 x i8> %tmp26 to <4 x i32>
244 …mage.sample.v2i32(<2 x i32> zeroinitializer, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0,…
251 …image.sample.v2i32(<2 x i32> <i32 1, i32 0>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0,…
[all …]
/external/swiftshader/third_party/LLVM/test/Transforms/SimplifyCFG/
D2009-01-19-UnconditionalTrappingConstantExpr.ll12 %tmp26 = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
13 br i1 %tmp26, label %bb6, label %bb2
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopStrengthReduce/X86/
Dlsr-filtering-scaledreg.ll53 %tmp26 = phi i8* [ %tmp29, %bb24 ], [ %tmp23, %bb18 ]
56 %tmp29 = getelementptr inbounds i8, i8* %tmp26, i64 1
57 store i8 %tmp28, i8* %tmp26, align 1
/external/llvm/test/Transforms/SimplifyCFG/
D2009-01-19-UnconditionalTrappingConstantExpr.ll17 %tmp26 = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
18 br i1 %tmp26, label %bb6, label %bb2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dpr30663.ll17 %tmp26 = fsub <4 x float> zeroinitializer, %tmp25
18 %tmp27 = bitcast <4 x float> %tmp26 to <4 x i32>

12345678910