Searched refs:tmp_count (Results 1 – 6 of 6) sorted by relevance
| /external/selinux/libsemanage/src/ |
| D | booleans_activedb.c | 27 unsigned int tmp_count = 0; in bool_read_list() local
51 tmp_count++; in bool_read_list()
72 *count = tmp_count; in bool_read_list()
84 for (i = 0; (unsigned int)i < tmp_count; i++) in bool_read_list()
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| D | database_llist.c | 341 unsigned int tmp_count; in dbase_llist_list() local
344 tmp_count = dbase->cache_sz; in dbase_llist_list()
345 if (tmp_count > 0) { in dbase_llist_list()
347 calloc(tmp_count, sizeof(record_t *)); in dbase_llist_list()
362 *count = tmp_count; in dbase_llist_list()
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| D | database_policydb.c | 403 unsigned int tmp_count; in dbase_policydb_list() local
410 dbase->policydb, &tmp_count) < 0) in dbase_policydb_list()
413 if (tmp_count > 0) { in dbase_policydb_list()
415 calloc(tmp_count, sizeof(record_t *)); in dbase_policydb_list()
431 *count = tmp_count; in dbase_policydb_list()
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| /external/u-boot/drivers/ddr/marvell/axp/ |
| D | ddr3_init.c | 199 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
230 tmp_count = 0; in ddr3_save_and_set_training_windows()
250 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
252 reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000; in ddr3_save_and_set_training_windows()
253 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
258 win_jump_index * tmp_count, 0); in ddr3_save_and_set_training_windows()
261 tmp_count++; in ddr3_save_and_set_training_windows()
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| D | ddr3_write_leveling.c | 187 u32 tmp_count, ecc, reg; in ddr3_wl_supplement() local
227 tmp_count = 0; in ddr3_wl_supplement()
264 tmp_count * (SDRAM_CS_SIZE + 1) + in ddr3_wl_supplement()
420 tmp_count++; in ddr3_wl_supplement()
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| /external/u-boot/drivers/ddr/marvell/a38x/ |
| D | mv_ddr_plat.c | 1143 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
1173 tmp_count = 0; in ddr3_save_and_set_training_windows()
1193 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
1195 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) & in ddr3_save_and_set_training_windows()
1197 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
1202 win_jump_index * tmp_count, 0); in ddr3_save_and_set_training_windows()
1204 tmp_count++; in ddr3_save_and_set_training_windows()
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