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/external/llvm/test/MC/Sparc/
Dsparc-v9-traps.s21 ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
22 !! tnz should be a synonym for tne
23 ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
24 ! CHECK: tne %icc, 82 ! encoding: [0x93,0xd0,0x20,0x52]
25 ! CHECK: tne %icc, %g1 + %i2 ! encoding: [0x93,0xd0,0x40,0x1a]
26 ! CHECK: tne %icc, %i5 + 41 ! encoding: [0x93,0xd7,0x60,0x29]
27 tne %icc, %i5
29 tne %icc, 82
30 tne %icc, %g1 + %i2
31 tne %icc, %i5 + 41
[all …]
Dsparc-traps.s21 ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
22 !! tnz should be a synonym for tne
23 ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
24 ! CHECK: tne 82 ! encoding: [0x93,0xd0,0x20,0x52]
25 ! CHECK: tne %g1 + %i2 ! encoding: [0x93,0xd0,0x40,0x1a]
26 ! CHECK: tne %i5 + 41 ! encoding: [0x93,0xd7,0x60,0x29]
27 tne %i5
29 tne 82
30 tne %g1 + %i2
31 tne %i5 + 41
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Sparc/
Dsparc-v9-traps.s21 ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
22 !! tnz should be a synonym for tne
23 ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
24 ! CHECK: tne %icc, 82 ! encoding: [0x93,0xd0,0x20,0x52]
25 ! CHECK: tne %icc, %g1 + %i2 ! encoding: [0x93,0xd0,0x40,0x1a]
26 ! CHECK: tne %icc, %i5 + 41 ! encoding: [0x93,0xd7,0x60,0x29]
27 tne %icc, %i5
29 tne %icc, 82
30 tne %icc, %g1 + %i2
31 tne %icc, %i5 + 41
[all …]
Dsparc-traps.s21 ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
22 !! tnz should be a synonym for tne
23 ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
24 ! CHECK: tne 82 ! encoding: [0x93,0xd0,0x20,0x52]
25 ! CHECK: tne %g1 + %i2 ! encoding: [0x93,0xd0,0x40,0x1a]
26 ! CHECK: tne %i5 + 41 ! encoding: [0x93,0xd7,0x60,0x29]
27 tne %i5
29 tne 82
30 tne %g1 + %i2
31 tne %i5 + 41
/external/llvm/test/MC/Mips/
Dmips-control-instructions.s33 # CHECK32: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
34 # CHECK32: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
64 # CHECK64: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
65 # CHECK64: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
98 tne $0,$3
99 tne $0,$3,1023
Dmicromips-trap-instructions.s17 # CHECK-EL: tne $8, $9 # encoding: [0x28,0x01,0x3c,0x0c]
32 # CHECK-EB: tne $8, $9 # encoding: [0x01,0x28,0x0c,0x3c]
44 tne $8, $9, 0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmips-control-instructions.s37 # CHECK32: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
38 # CHECK32: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
72 # CHECK64: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
73 # CHECK64: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
106 tne $0,$3
107 tne $0,$3,1023
Dmicromips-trap-instructions.s17 # CHECK-EL: tne $8, $9 # encoding: [0x28,0x01,0x3c,0x0c]
32 # CHECK-EB: tne $8, $9 # encoding: [0x01,0x28,0x0c,0x3c]
44 tne $8, $9, 0
Dmul-macro-variants.s76 # CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6]
92 # CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6]
104 # CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6]
115 # CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6]
142 # CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6]
154 # CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6]
/external/capstone/suite/MC/Mips/
Dmips-control-instructions-64.s.cs31 0x00,0x03,0x00,0x36 = tne $zero, $3
32 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
Dmips-control-instructions.s.cs31 0x00,0x03,0x00,0x36 = tne $zero, $3
32 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
Dmicromips-trap-instructions.s.cs7 0x28,0x01,0x3c,0x0c = tne $8, $9
Dmicromips-trap-instructions-EB.s.cs7 0x01,0x28,0x0c,0x3c = tne $8, $9
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid-wrong-error.s25 tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
26 tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
27 …tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid-wrong-error.s33 tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
34 tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
35 …tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
/external/llvm/test/MC/Mips/mips2/
Dvalid.s170 … tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
171 … tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc-v9.txt21 # CHECK: tne %icc, 82
78 # CHECK: tne %xcc, 82
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Sparc/
Dsparc-v9.txt21 # CHECK: tne %icc, 82
78 # CHECK: tne %xcc, 82
/external/llvm/test/MC/Mips/mips32/
Dvalid.s200 … tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
201 … tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s234 … tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
235 … tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s238 … tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
239 … tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s237 … tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
238 … tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s237 … tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
238 … tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/
Dvalid.s245 … tne $6, $17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
246 … tne $7, $8, 885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips2.s43 …tne $6,$17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
44 …tne $7,$8,885 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…

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