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Searched refs:training_result (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_debug.c188 memcpy(result, training_result, in hws_ddr3_tip_read_training_result()
201 return training_result[stage]; in ddr3_tip_get_result_ptr()
401 (training_result[INIT_CONTROLLER] in ddr3_tip_print_log()
408 (training_result[SET_LOW_FREQ] in ddr3_tip_print_log()
415 (training_result[LOAD_PATTERN] in ddr3_tip_print_log()
422 (training_result[SET_MEDIUM_FREQ] in ddr3_tip_print_log()
429 (training_result[WRITE_LEVELING] in ddr3_tip_print_log()
436 (training_result[LOAD_PATTERN_2] in ddr3_tip_print_log()
443 (training_result[READ_LEVELING] in ddr3_tip_print_log()
450 (training_result[WRITE_LEVELING_SUPP] in ddr3_tip_print_log()
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Dddr3_training_leveling.c85 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_read_leveling()
256 training_result[training_stage][if_id] = in ddr3_tip_dynamic_read_leveling()
330 if (training_result[training_stage][if_id] == TEST_FAILED) in ddr3_tip_dynamic_read_leveling()
460 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_per_bit_read_leveling()
738 training_result[training_stage][if_id] = TEST_FAILED; in ddr3_tip_dynamic_per_bit_read_leveling()
783 if (training_result[training_stage][if_id] == TEST_FAILED) in ddr3_tip_dynamic_per_bit_read_leveling()
852 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_write_leveling()
1136 training_result[training_stage][if_id] = in ddr3_tip_dynamic_write_leveling()
1190 if (training_result[training_stage][if_id] == TEST_FAILED) in ddr3_tip_dynamic_write_leveling()
1295 training_result[training_stage][if_id] = TEST_FAILED; in ddr3_tip_dynamic_write_leveling_supp()
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Dddr3_training_centralization.c54 enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; in ddr3_tip_centralization() local
129 PARAM_NOT_CARE, training_result); in ddr3_tip_centralization()
495 enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; in ddr3_tip_special_rx() local
542 PARAM_NOT_CARE, training_result); in ddr3_tip_special_rx()
Dddr3_training_pbs.c715 training_result[training_stage][if_id] in ddr3_tip_pbs()
722 training_result[ in ddr3_tip_pbs()
724 (training_result[training_stage] in ddr3_tip_pbs()
Dddr3_init.h95 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
Dddr3_training_bist.c226 enum hws_training_ip_stat training_result; in mv_ddr_tip_bist() local
233 TIP_ITERATION_NUM, pattern, EDGE_FP, CS_SINGLE, cs, &training_result); in mv_ddr_tip_bist()
Dddr3_training.c37 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]; variable
1116 training_result[training_stage][interface_num] = in ddr3_tip_if_polling()
1268 enum hws_result *flow_result = training_result[training_stage]; in ddr3_tip_freq_set()
1298 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_freq_set()
2616 training_result[stage][if_id] = NO_TEST_DONE; in ddr3_tip_ddr3_auto_tune()
2642 if (training_result[stage][if_id] == TEST_FAILED) in ddr3_tip_ddr3_auto_tune()
Dddr3_training_ip_engine.c852 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_load_all_pattern_to_mem()