| /external/mesa3d/prebuilt-intermediates/isl/ |
| D | isl_format_layout.c | 47 .txc = ISL_TXC_NONE,
67 .txc = ISL_TXC_NONE,
87 .txc = ISL_TXC_NONE,
107 .txc = ISL_TXC_NONE,
127 .txc = ISL_TXC_NONE,
147 .txc = ISL_TXC_NONE,
167 .txc = ISL_TXC_NONE,
187 .txc = ISL_TXC_NONE,
207 .txc = ISL_TXC_NONE,
227 .txc = ISL_TXC_NONE,
[all …]
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| /external/linux-kselftest/tools/testing/selftests/timers/ |
| D | freq-step.c | 90 struct timex txc; in reset_ntp_error() local
92 txc.modes = ADJ_SETOFFSET; in reset_ntp_error()
93 txc.time.tv_sec = 0; in reset_ntp_error()
94 txc.time.tv_usec = 0; in reset_ntp_error()
96 if (adjtimex(&txc) < 0) { in reset_ntp_error()
104 struct timex txc; in set_frequency() local
109 txc.modes = ADJ_TICK | ADJ_FREQUENCY; in set_frequency()
110 txc.tick = 1000000 / user_hz + tick_offset; in set_frequency()
111 txc.freq = (1e6 * freq - user_hz * tick_offset) * (1 << 16); in set_frequency()
113 if (adjtimex(&txc) < 0) { in set_frequency()
|
| /external/u-boot/doc/device-tree-bindings/net/ |
| D | micrel-ksz90x1.txt | 21 - txc-skew-ps : Skew control of TXC pad
44 The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
108 - txc-skew-ps : Skew control of TX clock pad
129 txc-skew-ps = <1800>;
139 txc-skew-ps = <1800>;
|
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nve4_compute.c | 114 PUSH_DATAh(push, screen->txc->offset); in nve4_screen_compute_setup()
115 PUSH_DATA (push, screen->txc->offset); in nve4_screen_compute_setup()
118 PUSH_DATAh(push, screen->txc->offset + 65536); in nve4_screen_compute_setup()
119 PUSH_DATA (push, screen->txc->offset + 65536); in nve4_screen_compute_setup()
201 struct nouveau_bo *txc = nvc0->screen->txc; in gm107_compute_validate_surfaces() local
217 PUSH_DATAh(push, txc->offset + (tic->id * 32)); in gm107_compute_validate_surfaces()
218 PUSH_DATA (push, txc->offset + (tic->id * 32)); in gm107_compute_validate_surfaces()
764 struct nouveau_bo *txc = nvc0->screen->txc; in nve4_compute_validate_textures() local
788 PUSH_DATAh(push, txc->offset + (tic->id * 32)); in nve4_compute_validate_textures()
789 PUSH_DATA (push, txc->offset + (tic->id * 32)); in nve4_compute_validate_textures()
|
| D | nvc0_compute.c | 106 PUSH_DATAh(push, screen->txc->offset); in nvc0_screen_compute_setup()
107 PUSH_DATA (push, screen->txc->offset); in nvc0_screen_compute_setup()
112 PUSH_DATAh(push, screen->txc->offset + 65536); in nvc0_screen_compute_setup()
113 PUSH_DATA (push, screen->txc->offset + 65536); in nvc0_screen_compute_setup()
|
| D | nvc0_screen.c | 566 nouveau_bo_ref(NULL, &screen->txc); in nvc0_screen_destroy()
1125 &screen->txc); in nvc0_screen_create()
1130 PUSH_DATAh(push, screen->txc->offset); in nvc0_screen_create()
1131 PUSH_DATA (push, screen->txc->offset); in nvc0_screen_create()
1143 PUSH_DATAh(push, screen->txc->offset + 65536); in nvc0_screen_create()
1144 PUSH_DATA (push, screen->txc->offset + 65536); in nvc0_screen_create()
|
| D | nvc0_tex.c | 471 nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32, in nvc0_update_tic()
505 nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32, in nvc0_validate_tic()
571 nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32, in nve4_validate_tic()
646 nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc, in nvc0_validate_tsc()
688 nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, in nve4_validate_tsc()
791 nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32, in nve4_create_texture_handle()
798 nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, in nve4_create_texture_handle()
1236 nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32, in gm107_validate_surfaces()
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_compute.c | 133 PUSH_DATAh(push, screen->txc->offset); in nv50_screen_compute_setup()
134 PUSH_DATA (push, screen->txc->offset); in nv50_screen_compute_setup()
140 PUSH_DATAh(push, screen->txc->offset + 65536); in nv50_screen_compute_setup()
141 PUSH_DATA (push, screen->txc->offset + 65536); in nv50_screen_compute_setup()
|
| D | nv50_tex.c | 243 struct nouveau_bo *txc = nv50->screen->txc; in nv50_validate_tic() local
270 PUSH_DATAh(push, txc->offset); in nv50_validate_tic()
271 PUSH_DATA (push, txc->offset); in nv50_validate_tic()
367 nv50_sifc_linear_u8(&nv50->base, nv50->screen->txc, in nv50_validate_tsc()
|
| D | nv50_screen.c | 494 nouveau_bo_ref(NULL, &screen->txc); in nv50_screen_destroy()
706 PUSH_DATAh(push, screen->txc->offset); in nv50_screen_init_hwctx()
707 PUSH_DATA (push, screen->txc->offset); in nv50_screen_init_hwctx()
711 PUSH_DATAh(push, screen->txc->offset + 65536); in nv50_screen_init_hwctx()
712 PUSH_DATA (push, screen->txc->offset + 65536); in nv50_screen_init_hwctx()
1029 &screen->txc); in nv50_screen_create()
|
| /external/u-boot/arch/arm/dts/ |
| D | sama5d3xcm.dtsi | 48 txc-skew-ps = <3000>;
62 txc-skew-ps = <3000>;
|
| D | sama5d3xcm_cmp.dtsi | 47 txc-skew-ps = <3000>;
61 txc-skew-ps = <3000>;
|
| D | socfpga_cyclone5_de1_soc.dts | 41 txc-skew-ps = <1860>;
|
| D | socfpga_cyclone5_de10_nano.dts | 43 txc-skew-ps = <1860>;
|
| D | socfpga_cyclone5_de0_nano_soc.dts | 41 txc-skew-ps = <1860>;
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| D | socfpga_stratix10_socdk.dts | 71 txc-skew-ps = <1860>; /* 960ps */
|
| D | socfpga_cyclone5_sockit.dts | 41 txc-skew-ps = <2600>;
|
| D | socfpga_cyclone5_socrates.dts | 45 txc-skew-ps = <2600>;
|
| D | socfpga_arria5_socdk.dts | 51 txc-skew-ps = <2600>;
|
| D | socfpga_cyclone5_is1.dts | 48 txc-skew-ps = <2600>;
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| D | socfpga_cyclone5_vining_fpga.dts | 41 txc-skew-ps = <2600>;
|
| /external/mesa3d/src/intel/isl/ |
| D | isl_gen7.c | 228 if (isl_format_get_layout(info->format)->txc == ISL_TXC_ASTC) in isl_gen6_filter_tiling()
232 if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS) in isl_gen6_filter_tiling()
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| D | isl_gen8.c | 104 if (fmtl->txc == ISL_TXC_CCS) { in isl_gen8_choose_image_alignment_el()
|
| D | isl_gen9.c | 111 if (fmtl->txc == ISL_TXC_CCS) { in isl_gen9_choose_image_alignment_el()
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| D | gen_format_layout.py | 170 self.txc = line[13].strip().upper() or 'NONE'
|