| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 284 define i32 @uhsax(i32 %a, i32 %b) nounwind {
285 ; CHECK-LABEL: uhsax
286 ; CHECK: uhsax r0, r0, r1
287 %tmp = call i32 @llvm.arm.uhsax(i32 %a, i32 %b)
463 declare i32 @llvm.arm.uhsax(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 82 M(uhsax) \
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| D | test-assembler-cond-rd-rn-rm-a32.cc | 83 M(uhsax) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 1091 0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6
1096 0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2867 uhsax r5, r6, r6
2878 @ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5]
2883 @ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5]
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3364 uhsax r5, r6, r6
3375 @ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5]
3380 @ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3420 uhsax r5, r6, r6
3431 @ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5]
3436 @ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3649 void uhsax(Condition cond, Register rd, Register rn, Register rm);
3650 void uhsax(Register rd, Register rn, Register rm) { uhsax(al, rd, rn, rm); } in uhsax() function
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| D | disasm-aarch32.h | 1379 void uhsax(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 3423 void Disassembler::uhsax(Condition cond, in uhsax() function in vixl::aarch32::Disassembler
21523 uhsax(CurrentCond(), in DecodeT32()
63386 uhsax(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 13131 void Assembler::uhsax(Condition cond, Register rd, Register rn, Register rm) { in uhsax() function in vixl::aarch32::Assembler
13151 Delegate(kUhsax, &Assembler::uhsax, cond, rd, rn, rm); in uhsax()
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| D | macro-assembler-aarch32.h | 4880 uhsax(cond, rd, rn, rm); in Uhsax()
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2237 # CHECK: uhsax r5, r6, r6
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2388 # CHECK: uhsax r5, r6, r6
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2388 # CHECK: uhsax r5, r6, r6
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3212 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
4987 def : MnemonicAlias<"uhsubaddx", "uhsax">;
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| D | ARMInstrThumb2.td | 1979 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3613 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
5697 def : MnemonicAlias<"uhsubaddx", "uhsax">;
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| D | ARMInstrThumb2.td | 2184 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3758 def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>;
5997 def : MnemonicAlias<"uhsubaddx", "uhsax">;
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| D | ARMInstrThumb2.td | 2252 def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1375 Mnemonic = "uhsax"; // "uhsubaddx"
7766 "uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005uhasx\005uhsax\007u"
9047 …{ 1588 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|F…
9048 …{ 1588 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1217 arm_uhsax, // llvm.arm.uhsax
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| D | IntrinsicImpl.inc | 1243 "llvm.arm.uhsax",
10121 1, // llvm.arm.uhsax
|