Searched refs:umaxv (Results 1 – 25 of 49) sorted by relevance
12
5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v010 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind28 ; CHECK: umaxv.4h h[[REG:[0-9]+]], v033 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind49 ; CHECK: umaxv.8h h[[REG:[0-9]+]], v054 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind70 ; CHECK: umaxv.16b b[[REG:[0-9]+]], v075 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v195 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)[all …]
41 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)43 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)45 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)53 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)55 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)185 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.8b187 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)188 %0 = trunc i32 %umaxv.i to i8194 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.4h196 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a)[all …]
58 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v066 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #382 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v089 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3105 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0112 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3128 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0135 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3195 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2197 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2
78 ; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b100 ; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h119 ; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s135 ; CHECK-NOT: umaxv324 ; CHECK: umaxv {{h[0-9]+}}, [[V0]]349 ; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
57 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v065 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #381 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v088 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3104 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0111 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3127 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0134 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3194 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2196 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2
47 ; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b55 ; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h63 ; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s139 ; CHECK: umaxv {{h[0-9]+}}, [[V0]]152 ; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
7 umaxv d0, p7, z31.b define12 umaxv d0, p7, z31.h define17 umaxv d0, p7, z31.s define22 umaxv v0.2d, p7, z31.d label31 umaxv h0, p8, z31.h label40 umaxv d0, p7, z31.d define46 umaxv d0, p7, z31.d define
10 umaxv b0, p7, z31.b label16 umaxv h0, p7, z31.h label22 umaxv s0, p7, z31.s label28 umaxv d0, p7, z31.d define
22 0x20,0xa8,0x30,0x2e = umaxv b0, v1.8b23 0x20,0xa8,0x30,0x6e = umaxv b0, v1.16b24 0x20,0xa8,0x70,0x2e = umaxv h0, v1.4h25 0x20,0xa8,0x70,0x6e = umaxv h0, v1.8h26 0x20,0xa8,0xb0,0x6e = umaxv s0, v1.4s
57 umaxv b0, v1.8b58 umaxv b0, v1.16b59 umaxv h0, v1.4h60 umaxv h0, v1.8h61 umaxv s0, v1.4s
3775 umaxv s0, v1.2s3797 umaxv d0, v1.2d define
3715 umaxv s0, v1.2s3737 umaxv d0, v1.2d define
97 ; CODE: umaxv b0, v0.8b106 ; CODE: umaxv b0, v0.16b115 ; CODE: umaxv h0, v0.4h124 ; CODE: umaxv h0, v0.8h133 ; CODE: umaxv s0, v0.4s
1905 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b1906 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b1907 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h1908 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h1909 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s
1904 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b ### {NEON} ###1905 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b ### {NEON} ###1906 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h ### {NEON} ###1907 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h ### {NEON} ###1908 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s ### {NEON} ###
1904 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b // Needs: NEON1905 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b // Needs: NEON1906 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h // Needs: NEON1907 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h // Needs: NEON1908 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s // Needs: NEON
1904 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b [1;35mNEON[0;m1905 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b [1;35mNEON[0;m1906 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h [1;35mNEON[0;m1907 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h [1;35mNEON[0;m1908 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s [1;35mNEON[0;m
2247 __ umaxv(b17, v30.V16B()); in GenerateTestSequenceNEON() local2248 __ umaxv(b23, v12.V8B()); in GenerateTestSequenceNEON() local2249 __ umaxv(h31, v15.V4H()); in GenerateTestSequenceNEON() local2250 __ umaxv(h15, v25.V8H()); in GenerateTestSequenceNEON() local2251 __ umaxv(s18, v21.V4S()); in GenerateTestSequenceNEON() local
2487 TEST_NEON(umaxv_0, umaxv(b0, v1.V8B()))2488 TEST_NEON(umaxv_1, umaxv(b0, v1.V16B()))2489 TEST_NEON(umaxv_2, umaxv(h0, v1.V4H()))2490 TEST_NEON(umaxv_3, umaxv(h0, v1.V8H()))2491 TEST_NEON(umaxv_4, umaxv(s0, v1.V4S()))
344 V(umaxv, Umaxv) \
11932 "uhsub\006umaddl\004umax\005umaxp\005umaxv\004umin\005uminp\005uminv\005"17950 …{ 5435 /* umaxv */, AArch64::UMAXV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1…17951 …{ 5435 /* umaxv */, AArch64::UMAXVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK…17952 …{ 5435 /* umaxv */, AArch64::UMAXVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_…17953 …{ 5435 /* umaxv */, AArch64::UMAXV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1…17954 …{ 5435 /* umaxv */, AArch64::UMAXVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK…17955 …{ 5435 /* umaxv */, AArch64::UMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1…17956 …{ 5435 /* umaxv */, AArch64::UMAXV_VPZ_B, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1…17957 …{ 5435 /* umaxv */, AArch64::UMAXVv16i8v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK…17958 …{ 5435 /* umaxv */, AArch64::UMAXVv8i8v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_F…[all …]