1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2015 Linaro 4 * Peter Griffin <peter.griffin@linaro.org> 5 */ 6 7 #ifndef __HI6220_ALWAYSON_H__ 8 #define __HI6220_ALWAYSON_H__ 9 10 #define ALWAYSON_CTRL_BASE 0xF7800000 11 12 struct alwayson_sc_regs { 13 u32 ctrl0; /*0x0*/ 14 u32 ctrl1; 15 u32 ctrl2; 16 17 u32 unknown; 18 19 u32 stat0; /*0x10*/ 20 u32 stat1; 21 u32 mcu_imctrl; 22 u32 mcu_imstat; 23 24 u32 unknown_1[9]; 25 26 u32 secondary_int_en0; /*0x44*/ 27 u32 secondary_int_statr0; 28 u32 secondary_int_statm0; 29 30 u32 unknown_2; 31 32 u32 mcu_wkup_int_en6; /*0x54*/ 33 u32 mcu_wkup_int_statr6; 34 u32 mcu_wkup_int_statm6; 35 36 u32 unknown_3; 37 38 u32 mcu_wkup_int_en5; /*0x64*/ 39 u32 mcu_wkup_int_statr5; 40 u32 mcu_wkup_int_statm5; 41 42 u32 unknown_4[9]; 43 44 u32 mcu_wkup_int_en4; /*0x94*/ 45 u32 mcu_wkup_int_statr4; 46 u32 mcu_wkup_int_statm4; 47 48 u32 unknown_5[2]; 49 50 u32 mcu_wkup_int_en0; /*0xa8*/ 51 u32 mcu_wkup_int_statr0; 52 u32 mcu_wkup_int_statm0; 53 54 u32 mcu_wkup_int_en1; /*0xb4*/ 55 u32 mcu_wkup_int_statr1; 56 u32 mcu_wkup_int_statm1; 57 58 u32 unknown_6; 59 60 u32 int_statr; /*0xc4*/ 61 u32 int_statm; 62 u32 int_clear; 63 64 u32 int_en_set; /*0xd0*/ 65 u32 int_en_dis; 66 u32 int_en_stat; 67 68 u32 unknown_7[2]; 69 70 u32 int_statr1; /*0xc4*/ 71 u32 int_statm1; 72 u32 int_clear1; 73 74 u32 int_en_set1; /*0xf0*/ 75 u32 int_en_dis1; 76 u32 int_en_stat1; 77 78 u32 unknown_8[53]; 79 80 u32 timer_en0; /*0x1d0*/ 81 u32 timer_en1; 82 83 u32 unknown_9[6]; 84 85 u32 timer_en4; /*0x1f0*/ 86 u32 timer_en5; 87 88 u32 unknown_10[130]; 89 90 u32 mcu_subsys_ctrl0; /*0x400*/ 91 u32 mcu_subsys_ctrl1; 92 u32 mcu_subsys_ctrl2; 93 u32 mcu_subsys_ctrl3; 94 u32 mcu_subsys_ctrl4; 95 u32 mcu_subsys_ctrl5; 96 u32 mcu_subsys_ctrl6; 97 u32 mcu_subsys_ctrl7; 98 99 u32 unknown_10_1[8]; 100 101 u32 mcu_subsys_stat0; /*0x440*/ 102 u32 mcu_subsys_stat1; 103 u32 mcu_subsys_stat2; 104 u32 mcu_subsys_stat3; 105 u32 mcu_subsys_stat4; 106 u32 mcu_subsys_stat5; 107 u32 mcu_subsys_stat6; 108 u32 mcu_subsys_stat7; 109 110 u32 unknown_11[116]; 111 112 u32 clk4_en; /*0x630*/ 113 u32 clk4_dis; 114 u32 clk4_stat; 115 116 u32 clk5_en; /*0x63c*/ 117 u32 clk5_dis; 118 u32 clk5_stat; 119 120 u32 unknown_12[42]; 121 122 u32 rst4_en; /*0x6f0*/ 123 u32 rst4_dis; 124 u32 rst4_stat; 125 126 u32 rst5_en; /*0x6fc*/ 127 u32 rst5_dis; 128 u32 rst5_stat; 129 130 u32 unknown_13[62]; 131 132 u32 pw_clk0_en; /*0x800*/ 133 u32 pw_clk0_dis; 134 u32 pw_clk0_stat; 135 136 u32 unknown_13_1; 137 138 u32 pw_rst0_en; /*0x810*/ 139 u32 pw_rst0_dis; 140 u32 pw_rst0_stat; 141 142 u32 unknown_14; 143 144 u32 pw_isoen0; /*0x820*/ 145 u32 pw_isodis0; 146 u32 pw_iso_stat0; 147 148 u32 unknown_14_1; 149 150 u32 pw_mtcmos_en0; /*0x830*/ 151 u32 pw_mtcmos_dis0; 152 u32 pw_mtcmos_stat0; 153 u32 pw_mtcmos_ack_stat0; 154 u32 pw_mtcmos_timeout_stat0; 155 156 u32 unknown_14_2[3]; 157 158 u32 pw_stat0; /*0x850*/ 159 u32 pw_stat1; 160 161 u32 unknown_15[10]; 162 163 u32 systest_stat; /*0x880*/ 164 165 u32 unknown_16[3]; 166 167 u32 systest_slicer_cnt0;/*0x890*/ 168 u32 systest_slicer_cnt1; 169 170 u32 unknown_17[12]; 171 172 u32 pw_ctrl1; /*0x8C8*/ 173 u32 pw_ctrl; 174 175 u32 mcpu_voteen; 176 u32 mcpu_votedis; 177 u32 mcpu_votestat; 178 179 u32 unknown_17_1; 180 181 u32 mcpu_vote_msk0; /*0x8E0*/ 182 u32 mcpu_vote_msk1; 183 u32 mcpu_votestat0_msk; 184 u32 mcpu_votestat1_msk; 185 186 u32 peri_voteen; /*0x8F0*/ 187 u32 peri_votedis; 188 u32 peri_votestat; 189 190 u32 unknown_17_2; 191 192 u32 peri_vote_msk0; /*0x900*/ 193 u32 peri_vote_msk1; 194 u32 peri_votestat0_msk; 195 u32 erpi_votestat1_msk; 196 u32 acpu_voteen; 197 u32 acpu_votedis; 198 u32 acpu_votestat; 199 200 u32 unknown_18; 201 202 u32 acpu_vote_msk0; /*0x920*/ 203 u32 acpu_vote_msk1; 204 u32 acpu_votestat0_msk; 205 u32 acpu_votestat1_msk; 206 u32 mcu_voteen; 207 u32 mcu_votedis; 208 u32 mcu_votestat; 209 210 u32 unknown_18_1; 211 212 u32 mcu_vote_msk0; /*0x940*/ 213 u32 mcu_vote_msk1; 214 u32 mcu_vote_votestat0_msk; 215 u32 mcu_vote_votestat1_msk; 216 217 u32 unknown_18_1_2[4]; 218 219 u32 mcu_vote_vote1en; /*0x960*/ 220 u32 mcu_vote_vote1dis; 221 u32 mcu_vote_vote1stat; 222 223 u32 unknown_18_2; 224 225 u32 mcu_vote_vote1_msk0;/*0x970*/ 226 u32 mcu_vote_vote1_msk1; 227 u32 mcu_vote_vote1stat0_msk; 228 u32 mcu_vote_vote1stat1_msk; 229 u32 mcu_vote_vote2en; 230 u32 mcu_vote_vote2dis; 231 u32 mcu_vote_vote2stat; 232 233 u32 unknown_18_3; 234 235 u32 mcu_vote2_msk0; /*0x990*/ 236 u32 mcu_vote2_msk1; 237 u32 mcu_vote2stat0_msk; 238 u32 mcu_vote2stat1_msk; 239 u32 vote_ctrl; 240 u32 vote_stat; /*0x9a4*/ 241 242 u32 unknown_19[342]; 243 244 u32 econum; /*0xf00*/ 245 246 u32 unknown_20_1[3]; 247 248 u32 scchipid; /*0xf10*/ 249 250 u32 unknown_20_2[2]; 251 252 u32 scsocid; /*0xf1c*/ 253 254 u32 unknown_20[48]; 255 256 u32 soc_fpga_rtl_def; /*0xfe0*/ 257 u32 soc_fpga_pr_def; 258 u32 soc_fpga_res_def0; 259 u32 soc_fpga_res_def1; /*0xfec*/ 260 }; 261 262 /* ctrl0 bit definitions */ 263 264 #define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004 265 #define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007 266 267 /* ctrl1 bit definitions */ 268 269 #define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0) 270 #define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1) 271 #define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2) 272 #define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3) 273 #define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4) 274 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6) 275 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7) 276 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8) 277 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9) 278 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10) 279 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11) 280 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12) 281 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13) 282 #define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15) 283 #define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16) 284 #define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17) 285 #define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18) 286 #define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19) 287 #define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20) 288 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22) 289 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23) 290 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24) 291 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25) 292 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26) 293 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27) 294 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28) 295 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29) 296 #define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31) 297 298 /* ctrl2 bit definitions */ 299 300 #define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26) 301 #define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27) 302 #define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28) 303 #define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29) 304 #define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30) 305 #define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31) 306 307 /* stat0 bit definitions */ 308 309 #define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25) 310 #define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26) 311 #define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27) 312 #define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28) 313 #define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29) 314 #define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30) 315 #define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31) 316 317 /* stat1 bit definitions */ 318 319 #define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0) 320 #define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16) 321 #define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17) 322 #define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19) 323 #define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20) 324 #define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27) 325 #define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28) 326 #define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29) 327 328 /* ctrl3 bit definitions */ 329 330 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 331 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 332 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3) 333 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4) 334 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8) 335 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9) 336 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10) 337 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11) 338 339 /* clk4_en bit definitions */ 340 341 #define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0) 342 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3) 343 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4) 344 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5) 345 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6) 346 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7) 347 #define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8) 348 #define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9) 349 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10) 350 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11) 351 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12) 352 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13) 353 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14) 354 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15) 355 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16) 356 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17) 357 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18) 358 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19) 359 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20) 360 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21) 361 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22) 362 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23) 363 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24) 364 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25) 365 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26) 366 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27) 367 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28) 368 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29) 369 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30) 370 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31) 371 372 /* clk5_en bit definitions */ 373 374 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0) 375 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1) 376 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2) 377 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3) 378 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16) 379 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17) 380 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18) 381 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19) 382 383 /* rst4_dis bit definitions */ 384 385 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0) 386 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1) 387 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2) 388 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3) 389 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4) 390 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5) 391 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6) 392 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7) 393 #define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8) 394 #define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9) 395 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10) 396 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12) 397 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13) 398 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14) 399 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15) 400 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16) 401 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17) 402 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18) 403 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19) 404 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20) 405 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21) 406 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22) 407 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23) 408 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24) 409 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25) 410 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26) 411 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27) 412 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28) 413 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29) 414 #define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30) 415 416 #define PCLK_TIMER1 (1 << 16) 417 #define PCLK_TIMER0 (1 << 15) 418 419 #endif /* __HI6220_ALWAYSON_H__ */ 420