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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dudivrem-change-width.ll32 ; CHECK-NEXT: [[TMP1:%.*]] = urem i8 %a, %b
37 %udiv = urem i32 %za, %zb
44 ; CHECK-NEXT: [[TMP1:%.*]] = urem <2 x i8> %a, %b
49 %udiv = urem <2 x i32> %za, %zb
109 ; CHECK-NEXT: [[TMP1:%.*]] = urem i8 %a, %b
115 %urem = urem i32 %za, %zb
116 ret i32 %urem
121 ; CHECK-NEXT: [[TMP1:%.*]] = urem <2 x i8> %a, %b
127 %urem = urem <2 x i32> %za, %zb
128 ret <2 x i32> %urem
[all …]
Dadd4.ll8 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136
12 %tmp = urem i64 %x, 299
14 %tmp2 = urem i64 %tmp1, 64
23 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
29 %tmp2 = urem i64 %tmp1, 9
60 %tmp = urem i64 %x, 299
62 %tmp2 = urem i64 %tmp1, 64
74 %tmp = urem i64 %x, 299
76 %tmp2 = urem i64 %tmp1, 64
88 %tmp = urem i32 %x, 299
[all …]
Dvector-urem.ll9 %1 = urem <4 x i32> %a0, <i32 2, i32 2, i32 2, i32 2>
18 %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
26 %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 undef>
36 %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %a0
46 %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 undef>, %a0
57 %1 = urem <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3>
68 %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
76 %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef>
Drem.ll28 ; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[X1:%.*]], [[Y2:%.*]]
46 %rem = urem i8 %x, 129
57 %rem = urem i5 %x, -1
68 %rem = urem i8 %y, %s
79 %rem = urem <2 x i8> %y, %s
90 %rem = urem <2 x i4> %x, <i4 13, i4 13>
96 ; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[X:%.*]], [[Y:%.*]]
118 ; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[X:%.*]], [[Y:%.*]]
130 ; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[X:%.*]], 3
180 %B = urem i32 %A, 8
[all …]
/external/llvm/test/CodeGen/X86/
Durem-power-of-two.ll13 %urem = urem i64 %x, 32
14 ret i64 %urem
30 %urem = urem i25 %x, %shl
31 ret i25 %urem
49 %urem = urem i16 %x, %shr
50 ret i16 %urem
67 %urem = urem i8 %x, %and
68 ret i8 %urem
79 %urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
80 ret <4 x i32> %urem
Drem_crash.ll7 %1 = urem i8 %x, 10
31 %1 = urem i8 %x, 10
39 %1 = urem i16 %x, 10
63 %1 = urem i16 %x, 10
71 %1 = urem i32 %x, 10
95 %1 = urem i32 %x, 10
103 %1 = urem i64 %x, 10
127 %1 = urem i64 %x, 10
135 %1 = urem i8 %x, 10
159 %1 = urem i8 %x, 10
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Durem-power-of-two.ll20 %urem = urem i64 %x, 32
21 ret i64 %urem
45 %urem = urem i25 %x, %shl
46 ret i25 %urem
72 %urem = urem i16 %x, %shr
73 ret i16 %urem
100 %urem = urem i8 %x, %and
101 ret i8 %urem
116 %urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
117 ret <4 x i32> %urem
[all …]
Drem_crash.ll7 %1 = urem i8 %x, 10
31 %1 = urem i8 %x, 10
39 %1 = urem i16 %x, 10
63 %1 = urem i16 %x, 10
71 %1 = urem i32 %x, 10
95 %1 = urem i32 %x, 10
103 %1 = urem i64 %x, 10
127 %1 = urem i64 %x, 10
135 %1 = urem i8 %x, 10
159 %1 = urem i8 %x, 10
[all …]
Dcombine-urem.ll6 ; fold (urem x, 1) -> 0
12 %1 = urem i32 %x, 1
26 %1 = urem <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
30 ; fold (urem x, -1) -> select((icmp eq x, -1), 0, x)
38 %1 = urem i32 %x, -1
57 %1 = urem <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
61 ; fold (urem x, INT_MIN) -> (and x, ~INT_MIN)
68 %1 = urem i32 %x, -2147483648
88 %1 = urem <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
92 ; TODO fold (urem x, x) -> 0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/CorrelatedValuePropagation/
Durem.ll17 ; CHECK: urem i16
18 %div = urem i32 %n, 100
32 ; CHECK: urem i32 %n, 100
33 %div = urem i32 %n, 100
49 ; CHECK: urem i16
50 %div = urem i32 %m, %n
66 ; CHECK: urem i32 %m, %n
67 %div = urem i32 %m, %n
77 ; CHECK: urem i8
78 %div = urem i32 %trunc, 42
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Drem.ll8 %B = urem i32 0, %A
24 %B = urem <2 x i32> <i32 undef, i32 0>, %A
42 %rem = urem <2 x i8> <i8 1, i8 2>, <i8 42, i8 0>
58 %rem = urem <2 x i8> %x, <i8 0, i8 42>
74 %rem = urem <2 x i8> %x, <i8 undef, i8 42>
94 %rem = urem <2 x i1> %x, %y
103 %r = urem <2 x i32> %y, %ext
130 %rem = urem i32 %x, %rhs
146 ; CHECK-NEXT: [[MOD:%.*]] = urem i32 [[X:%.*]], [[N:%.*]]
149 %mod = urem i32 %x, %n
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ScalarEvolution/
Durem-0.ll5 %t0 = urem i8 %a, 27
6 ; CHECK: %t0 = urem i8 %a, 27
13 %t1 = urem i8 %a, 1
14 ; CHECK: %t1 = urem i8 %a, 1
21 %t2 = urem i8 %a, 32
22 ; CHECK: %t2 = urem i8 %a, 32
29 %t3 = urem i8 %a, 2
30 ; CHECK: %t3 = urem i8 %a, 2
/external/llvm/test/Analysis/CostModel/ARM/
Ddivrem.ll341 ; CHECK: cost of 40 {{.*}} urem
343 %1 = urem <2 x i8> %a, %b
348 ; CHECK: cost of 40 {{.*}} urem
350 %1 = urem <2 x i16> %a, %b
355 ; CHECK: cost of 40 {{.*}} urem
357 %1 = urem <2 x i32> %a, %b
362 ; CHECK: cost of 40 {{.*}} urem
364 %1 = urem <2 x i64> %a, %b
369 ; CHECK: cost of 80 {{.*}} urem
371 %1 = urem <4 x i8> %a, %b
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/ARM/
Ddivrem.ll341 ; CHECK: cost of 40 {{.*}} urem
343 %1 = urem <2 x i8> %a, %b
348 ; CHECK: cost of 40 {{.*}} urem
350 %1 = urem <2 x i16> %a, %b
355 ; CHECK: cost of 40 {{.*}} urem
357 %1 = urem <2 x i32> %a, %b
362 ; CHECK: cost of 40 {{.*}} urem
364 %1 = urem <2 x i64> %a, %b
369 ; CHECK: cost of 80 {{.*}} urem
371 %1 = urem <4 x i8> %a, %b
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Drem_crash.ll6 %1 = urem i8 %x, 10
30 %1 = urem i8 %x, 10
38 %1 = urem i16 %x, 10
62 %1 = urem i16 %x, 10
70 %1 = urem i32 %x, 10
94 %1 = urem i32 %x, 10
102 %1 = urem i64 %x, 10
126 %1 = urem i64 %x, 10
134 %1 = urem i8 %x, 10
158 %1 = urem i8 %x, 10
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Drem_crash.ll6 %1 = urem i8 %x, 10
30 %1 = urem i8 %x, 10
38 %1 = urem i16 %x, 10
62 %1 = urem i16 %x, 10
70 %1 = urem i32 %x, 10
94 %1 = urem i32 %x, 10
102 %1 = urem i64 %x, 10
126 %1 = urem i64 %x, 10
134 %1 = urem i8 %x, 10
158 %1 = urem i8 %x, 10
[all …]
/external/llvm/test/CodeGen/AArch64/
Drem_crash.ll6 %1 = urem i8 %x, 10
30 %1 = urem i8 %x, 10
38 %1 = urem i16 %x, 10
62 %1 = urem i16 %x, 10
70 %1 = urem i32 %x, 10
94 %1 = urem i32 %x, 10
102 %1 = urem i64 %x, 10
126 %1 = urem i64 %x, 10
134 %1 = urem i8 %x, 10
158 %1 = urem i8 %x, 10
[all …]
/external/llvm/test/CodeGen/ARM/
Drem_crash.ll6 %1 = urem i8 %x, 10
30 %1 = urem i8 %x, 10
38 %1 = urem i16 %x, 10
62 %1 = urem i16 %x, 10
70 %1 = urem i32 %x, 10
94 %1 = urem i32 %x, 10
102 %1 = urem i64 %x, 10
126 %1 = urem i64 %x, 10
134 %1 = urem i8 %x, 10
158 %1 = urem i8 %x, 10
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/X86/
Drem.ll76 define i32 @urem() {
77 ; CHECK-LABEL: 'urem'
78 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = urem i64 undef, und…
79 ; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V2i64 = urem <2 x i64> u…
80 ; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V4i64 = urem <4 x i64> u…
81 ; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V8i64 = urem <8 x i64> …
82 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = urem i32 undef, und…
83 ; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V4i32 = urem <4 x i32> u…
84 ; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V8i32 = urem <8 x i32> …
85 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i32 = urem <16 x i32…
[all …]
/external/llvm/test/Transforms/InstCombine/
Drem.ll24 %B = urem i32 %A, 8
33 %B = urem <2 x i32> %A, <i32 8, i32 8>
42 %B = urem <2 x i19> %A, <i19 8, i19 8>
61 %R = urem i32 %X, %V
74 %V = urem i32 %X, %Amt
105 %C = urem i32 %B, 32
115 %tmp.5 = urem i64 %tmp.3, 4
125 %tmp.5 = urem i32 %tmp.3, 4
153 %urem = urem i64 %x, %zext
154 ret i64 %urem
[all …]
/external/llvm/test/Transforms/InstSimplify/
Drem.ll18 %rem = urem i32 %x, %rhs
34 ; CHECK: [[MOD:%.*]] = urem i32 %x, %n
37 %mod = urem i32 %x, %n
38 %mod1 = urem i32 %mod, %n
45 ; CHECK-NEXT: [[MOD1:%.*]] = urem i32 [[MOD]], %n
49 %mod1 = urem i32 %mod, %n
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/
Dint-arith.ll282 define void @urem() {
283 %res0 = urem i8 undef, undef
284 %res1 = urem i16 undef, undef
285 %res2 = urem i32 undef, undef
286 %res3 = urem i64 undef, undef
287 %res4 = urem <2 x i8> undef, undef
288 %res5 = urem <2 x i16> undef, undef
289 %res6 = urem <2 x i32> undef, undef
290 %res7 = urem <2 x i64> undef, undef
291 %res8 = urem <4 x i8> undef, undef
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Durem.ll5 ; The code generated by urem is long and complex and may frequently
7 ; when it gets a v2i32/v4i32 urem
16 %result = urem i32 %a, %b
31 %result = urem i32 %num, 7
43 %result = urem <2 x i32> %a, %b
55 %result = urem <4 x i32> %a, %b
67 %result = urem i64 %a, %b
79 %result = urem <2 x i64> %a, %b
91 %result = urem <4 x i64> %a, %b
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Durem.ll5 ; The code generated by urem is long and complex and may frequently
7 ; when it gets a v2i32/v4i32 urem
16 %result = urem i32 %a, %b
31 %result = urem i32 %num, 7
43 %result = urem <2 x i32> %a, %b
55 %result = urem <4 x i32> %a, %b
67 %result = urem i64 %a, %b
79 %result = urem <2 x i64> %a, %b
91 %result = urem <4 x i64> %a, %b
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dudivrem-change-width.ll19 %div = urem i32 %conv, %conv2
23 ; CHECK: urem i8 %a, %b
39 %div = urem i32 %conv, %conv2
42 ; CHECK: urem i8 %a, %b
57 %div = urem i32 %conv, 10
60 ; CHECK: urem i8 %a, 10

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