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Searched refs:ushll2 (Results 1 – 25 of 40) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-shift-left-long.s28 ushll2 v0.8h, v1.16b, #3
29 ushll2 v0.4s, v1.8h, #3
30 ushll2 v0.2d, v1.4s, #3
Darm64-advsimd.s1603 ushll2.8h v0, v0, #2
1605 ushll2.4s v0, v0, #4
1607 ushll2.2d v0, v0, #6
1775 ; CHECK: ushll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x6f]
1777 ; CHECK: ushll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x6f]
1779 ; CHECK: ushll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x6f]
1861 ushll2 v10.8h, v3.16b, #6
1862 ushll2 v11.4s, v4.8h, #5
1863 ushll2 v12.2d, v5.4s, #4
1923 ; CHECK: ushll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x6f]
[all …]
Dneon-diagnostics.s1334 ushll2 v1.4s, v25.4s, #7
1343 ushll2 v0.2d, v1.4s, #33
/external/llvm/test/MC/AArch64/
Dneon-shift-left-long.s28 ushll2 v0.8h, v1.16b, #3
29 ushll2 v0.4s, v1.8h, #3
30 ushll2 v0.2d, v1.4s, #3
Darm64-advsimd.s1603 ushll2.8h v0, v0, #2
1605 ushll2.4s v0, v0, #4
1607 ushll2.2d v0, v0, #6
1775 ; CHECK: ushll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x6f]
1777 ; CHECK: ushll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x6f]
1779 ; CHECK: ushll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x6f]
1861 ushll2 v10.8h, v3.16b, #6
1862 ushll2 v11.4s, v4.8h, #5
1863 ushll2 v12.2d, v5.4s, #4
1923 ; CHECK: ushll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x6f]
[all …]
Dneon-diagnostics.s1329 ushll2 v1.4s, v25.4s, #7
1338 ushll2 v0.2d, v1.4s, #33
/external/capstone/suite/MC/AArch64/
Dneon-shift-left-long.s.cs11 0x20,0xa4,0x0b,0x6f = ushll2 v0.8h, v1.16b, #3
12 0x20,0xa4,0x13,0x6f = ushll2 v0.4s, v1.8h, #3
13 0x20,0xa4,0x23,0x6f = ushll2 v0.2d, v1.4s, #3
/external/llvm/test/CodeGen/AArch64/
Darm64-subvector-extend.ll27 ; CHECK-NEXT: ushll2.8h v1, v0, #0
65 ; CHECK-NEXT: ushll2.4s v1, v0, #0
84 ; CHECK-NEXT: ushll2.4s v1, v0, #0
107 ; CHECK-NEXT: ushll2.2d v1, v0, #0
126 ; CHECK-NEXT: ushll2.2d v1, v0, #0
Dneon-shift-left-long.ll80 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
89 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
98 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
173 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
181 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
189 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
Dfp16-v8-instructions.ll312 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
326 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
Darm64-vshift.ll1167 ;CHECK: ushll2.8h v0, {{v[0-9]+}}, #1
1177 ;CHECK: ushll2.4s v0, {{v[0-9]+}}, #1
1187 ;CHECK: ushll2.2d v0, {{v[0-9]+}}, #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-subvector-extend.ll27 ; CHECK-NEXT: ushll2.8h v1, v0, #0
65 ; CHECK-NEXT: ushll2.4s v1, v0, #0
84 ; CHECK-NEXT: ushll2.4s v1, v0, #0
107 ; CHECK-NEXT: ushll2.2d v1, v0, #0
126 ; CHECK-NEXT: ushll2.2d v1, v0, #0
Dneon-shift-left-long.ll80 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
89 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
98 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
173 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
181 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
189 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
Dfp16-v8-instructions.ll336 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
350 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2178 # CHECK: ushll2.8h v0, v0, #0x2
2180 # CHECK: ushll2.4s v0, v0, #0x4
2182 # CHECK: ushll2.2d v0, v0, #0x6
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2178 # CHECK: ushll2.8h v0, v0, #0x2
2180 # CHECK: ushll2.4s v0, v0, #0x4
2182 # CHECK: ushll2.2d v0, v0, #0x6
/external/v8/src/arm64/
Dmacro-assembler-arm64.h1076 V(ushll2, Ushll2) \
Dsimulator-arm64.h1744 LogicVRegister ushll2(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.cc2068 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) { in ushll2() function in v8::internal::Assembler
2078 ushll2(vd, vn, 0); in uxtl2()
Dassembler-arm64.h2746 void ushll2(const VRegister& vd, const VRegister& vn, int shift);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour2085 0x~~~~~~~~~~~~~~~~ 6f27a7a8 ushll2 v8.2d, v29.4s, #7
2086 0x~~~~~~~~~~~~~~~~ 6f12a53d ushll2 v29.4s, v9.8h, #2
2087 0x~~~~~~~~~~~~~~~~ 6f0ea705 ushll2 v5.8h, v24.16b, #6
Dlog-disasm2085 0x~~~~~~~~~~~~~~~~ 6f27a7a8 ushll2 v8.2d, v29.4s, #7
2086 0x~~~~~~~~~~~~~~~~ 6f12a53d ushll2 v29.4s, v9.8h, #2
2087 0x~~~~~~~~~~~~~~~~ 6f0ea705 ushll2 v5.8h, v24.16b, #6
Dlog-cpufeatures-custom2084 0x~~~~~~~~~~~~~~~~ 6f27a7a8 ushll2 v8.2d, v29.4s, #7 ### {NEON} ###
2085 0x~~~~~~~~~~~~~~~~ 6f12a53d ushll2 v29.4s, v9.8h, #2 ### {NEON} ###
2086 0x~~~~~~~~~~~~~~~~ 6f0ea705 ushll2 v5.8h, v24.16b, #6 ### {NEON} ###
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2427 __ ushll2(v8.V2D(), v29.V4S(), 7); in GenerateTestSequenceNEON() local
2428 __ ushll2(v29.V4S(), v9.V8H(), 2); in GenerateTestSequenceNEON() local
2429 __ ushll2(v5.V8H(), v24.V16B(), 6); in GenerateTestSequenceNEON() local
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2554 LogicVRegister ushll2(VectorFormat vform,

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