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/external/libaom/libaom/aom_dsp/simd/
Dv128_intrinsics.h24 typedef c_v128 v128; typedef
26 SIMD_INLINE uint32_t v128_low_u32(v128 a) { return c_v128_low_u32(a); } in v128_low_u32()
27 SIMD_INLINE v64 v128_low_v64(v128 a) { return c_v128_low_v64(a); } in v128_low_v64()
28 SIMD_INLINE v64 v128_high_v64(v128 a) { return c_v128_high_v64(a); } in v128_high_v64()
29 SIMD_INLINE v128 v128_from_64(uint64_t hi, uint64_t lo) { in v128_from_64()
32 SIMD_INLINE v128 v128_from_v64(v64 hi, v64 lo) { in v128_from_v64()
35 SIMD_INLINE v128 v128_from_32(uint32_t a, uint32_t b, uint32_t c, uint32_t d) { in v128_from_32()
39 SIMD_INLINE v128 v128_load_unaligned(const void *p) { in v128_load_unaligned()
42 SIMD_INLINE v128 v128_load_aligned(const void *p) { in v128_load_aligned()
46 SIMD_INLINE void v128_store_unaligned(void *p, v128 a) { in v128_store_unaligned()
[all …]
Dv128_intrinsics_x86.h18 typedef __m128i v128; typedef
20 SIMD_INLINE uint32_t v128_low_u32(v128 a) { in v128_low_u32()
24 SIMD_INLINE v64 v128_low_v64(v128 a) { in v128_low_v64()
28 SIMD_INLINE v64 v128_high_v64(v128 a) { return _mm_srli_si128(a, 8); } in v128_high_v64()
30 SIMD_INLINE v128 v128_from_v64(v64 a, v64 b) { in v128_from_v64()
34 SIMD_INLINE v128 v128_from_64(uint64_t a, uint64_t b) { in v128_from_64()
38 SIMD_INLINE v128 v128_from_32(uint32_t a, uint32_t b, uint32_t c, uint32_t d) { in v128_from_32()
42 SIMD_INLINE v128 v128_load_aligned(const void *p) { in v128_load_aligned()
46 SIMD_INLINE v128 v128_load_unaligned(const void *p) { in v128_load_unaligned()
54 SIMD_INLINE void v128_store_aligned(void *p, v128 a) { in v128_store_aligned()
[all …]
Dv128_intrinsics_arm.h19 typedef int64x2_t v128; typedef
21 SIMD_INLINE uint32_t v128_low_u32(v128 a) { in v128_low_u32()
25 SIMD_INLINE v64 v128_low_v64(v128 a) { return vget_low_s64(a); } in v128_low_v64()
27 SIMD_INLINE v64 v128_high_v64(v128 a) { return vget_high_s64(a); } in v128_high_v64()
29 SIMD_INLINE v128 v128_from_v64(v64 a, v64 b) { return vcombine_s64(b, a); } in v128_from_v64()
31 SIMD_INLINE v128 v128_from_64(uint64_t a, uint64_t b) { in v128_from_64()
35 SIMD_INLINE v128 v128_from_32(uint32_t a, uint32_t b, uint32_t c, uint32_t d) { in v128_from_32()
39 SIMD_INLINE v128 v128_load_aligned(const void *p) { in v128_load_aligned()
43 SIMD_INLINE v128 v128_load_unaligned(const void *p) { in v128_load_unaligned()
47 SIMD_INLINE void v128_store_aligned(void *p, v128 r) { in v128_store_aligned()
[all …]
Dv256_intrinsics_c.h32 c_v128 v128[2]; member
41 SIMD_INLINE c_v128 c_v256_low_v128(c_v256 a) { return a.v128[0]; } in c_v256_low_v128()
43 SIMD_INLINE c_v128 c_v256_high_v128(c_v256 a) { return a.v128[1]; } in c_v256_high_v128()
47 t.v128[1] = hi; in c_v256_from_v128()
48 t.v128[0] = lo; in c_v256_from_v128()
134 return c_v128_dotp_su8(a.v128[1], b.v128[1]) + in c_v256_dotp_su8()
135 c_v128_dotp_su8(a.v128[0], b.v128[0]); in c_v256_dotp_su8()
139 return c_v128_dotp_s16(a.v128[1], b.v128[1]) + in c_v256_dotp_s16()
140 c_v128_dotp_s16(a.v128[0], b.v128[0]); in c_v256_dotp_s16()
144 return c_v128_dotp_s32(a.v128[1], b.v128[1]) + in c_v256_dotp_s32()
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Dv256_intrinsics_x86.h44 SIMD_INLINE v128 v256_low_v128(v256 a) { return _mm256_castsi256_si128(a); } in v256_low_v128()
46 SIMD_INLINE v128 v256_high_v128(v256 a) { in v256_high_v128()
50 SIMD_INLINE v256 v256_from_v128(v128 a, v128 b) { in v256_from_v128()
197 SIMD_INLINE v256 v256_zip_8(v128 a, v128 b) { in v256_zip_8()
201 SIMD_INLINE v256 v256_zip_16(v128 a, v128 b) { in v256_zip_16()
205 SIMD_INLINE v256 v256_zip_32(v128 a, v128 b) { in v256_zip_32()
259 SIMD_INLINE v256 v256_unpack_u8_s16(v128 a) { in v256_unpack_u8_s16()
275 SIMD_INLINE v256 v256_unpack_s8_s16(v128 a) { in v256_unpack_s8_s16()
313 SIMD_INLINE v256 v256_unpack_u16_s32(v128 a) { in v256_unpack_u16_s32()
317 SIMD_INLINE v256 v256_unpack_s16_s32(v128 a) { in v256_unpack_s16_s32()
[all …]
Dv256_intrinsics_v128.h27 v128 val[2];
37 SIMD_INLINE v128 v256_low_v128(v256 a) { return a.val[0]; } in v256_low_v128()
39 SIMD_INLINE v128 v256_high_v128(v256 a) { return a.val[1]; } in v256_high_v128()
41 SIMD_INLINE v256 v256_from_v128(v128 hi, v128 lo) { in v256_from_v128()
81 v128 t = v128_dup_8(x); in v256_dup_8()
86 v128 t = v128_dup_16(x); in v256_dup_16()
91 v128 t = v128_dup_32(x); in v256_dup_32()
96 v128 t = v128_dup_64(x); in v256_dup_64()
276 SIMD_INLINE v256 v256_mul_s16(v128 a, v128 b) { in v256_mul_s16()
277 v128 lo_bits = v128_mullo_s16(a, b); in v256_mul_s16()
[all …]
Dv256_intrinsics.h30 SIMD_INLINE v128 v256_low_v128(v256 a) { return c_v256_low_v128(a); } in v256_low_v128()
31 SIMD_INLINE v128 v256_high_v128(v256 a) { return c_v256_high_v128(a); } in v256_high_v128()
32 SIMD_INLINE v256 v256_from_v128(v128 hi, v128 lo) { in v256_from_v128()
119 SIMD_INLINE v256 v256_mul_s16(v128 a, v128 b) { return c_v256_mul_s16(a, b); } in v256_mul_s16()
166 SIMD_INLINE v256 v256_zip_8(v128 a, v128 b) { return c_v256_zip_8(a, b); } in v256_zip_8()
167 SIMD_INLINE v256 v256_zip_16(v128 a, v128 b) { return c_v256_zip_16(a, b); } in v256_zip_16()
168 SIMD_INLINE v256 v256_zip_32(v128 a, v128 b) { return c_v256_zip_32(a, b); } in v256_zip_32()
193 SIMD_INLINE v256 v256_unpack_u8_s16(v128 a) { return c_v256_unpack_u8_s16(a); } in v256_unpack_u8_s16()
200 SIMD_INLINE v256 v256_unpack_s8_s16(v128 a) { return c_v256_unpack_s8_s16(a); } in v256_unpack_s8_s16()
219 SIMD_INLINE v256 v256_unpack_u16_s32(v128 a) { in v256_unpack_u16_s32()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/WebAssembly/
Dsimd-arith.ll20 ; SIMD128: .param v128, v128{{$}}
21 ; SIMD128: .result v128{{$}}
31 ; SIMD128: .param v128, v128{{$}}
32 ; SIMD128: .result v128{{$}}
42 ; SIMD128: .param v128, v128{{$}}
43 ; SIMD128: .result v128{{$}}
56 ; SIMD128: .param v128, v128{{$}}
57 ; SIMD128: .result v128{{$}}
67 ; SIMD128: .param v128, v128{{$}}
68 ; SIMD128: .result v128{{$}}
[all …]
/external/libaom/libaom/av1/common/
Dcdef_block_simd.h25 static INLINE v128 fold_mul_and_sum(v128 partiala, v128 partialb, v128 const1, in fold_mul_and_sum()
26 v128 const2) { in fold_mul_and_sum()
27 v128 tmp; in fold_mul_and_sum()
46 static INLINE v128 hsum4(v128 x0, v128 x1, v128 x2, v128 x3) { in hsum4()
47 v128 t0, t1, t2, t3; in hsum4()
61 static INLINE v128 compute_directions(v128 lines[8], int32_t tmp_cost1[4]) { in compute_directions()
62 v128 partial4a, partial4b, partial5a, partial5b, partial7a, partial7b; in compute_directions()
63 v128 partial6; in compute_directions()
64 v128 tmp; in compute_directions()
132 static INLINE void array_reverse_transpose_8x8(v128 *in, v128 *res) { in array_reverse_transpose_8x8()
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/external/libaom/libaom/test/
Dsimd_cmp_impl.h140 v128 imm_v128_shl_n_byte(v128 a) { in imm_v128_shl_n_byte()
144 v128 imm_v128_shr_n_byte(v128 a) { in imm_v128_shr_n_byte()
148 v128 imm_v128_shl_n_8(v128 a) { in imm_v128_shl_n_8()
152 v128 imm_v128_shr_n_u8(v128 a) { in imm_v128_shr_n_u8()
156 v128 imm_v128_shr_n_s8(v128 a) { in imm_v128_shr_n_s8()
160 v128 imm_v128_shl_n_16(v128 a) { in imm_v128_shl_n_16()
164 v128 imm_v128_shr_n_u16(v128 a) { in imm_v128_shr_n_u16()
168 v128 imm_v128_shr_n_s16(v128 a) { in imm_v128_shr_n_s16()
172 v128 imm_v128_shl_n_32(v128 a) { in imm_v128_shl_n_32()
176 v128 imm_v128_shr_n_u32(v128 a) { in imm_v128_shr_n_u32()
[all …]
/external/libunwind_llvm/src/
DRegisters.hpp24 struct v128 { uint32_t vec[4]; }; struct
54 v128 getVectorRegister(int num) const;
55 void setVectorRegister(int num, v128 value);
236 inline v128 Registers_x86::getVectorRegister(int) const { in getVectorRegister()
240 inline void Registers_x86::setVectorRegister(int, v128) { in setVectorRegister() argument
261 v128 getVectorRegister(int num) const;
262 void setVectorRegister(int num, v128 value);
314 v128 _xmm[16];
538 inline v128 Registers_x86_64::getVectorRegister(int regNum) const { in getVectorRegister()
548 inline void Registers_x86_64::setVectorRegister(int regNum, v128 value) { in setVectorRegister()
[all …]
/external/llvm/test/CodeGen/X86/
Dfp128-i128.ll208 @v128 = common global i128 0, align 16
212 ; unsigned __int128 v128, v128_2;
214 ; v128 = ((v128 << 96) | v128_2);
218 %0 = load i128, i128* @v128, align 16
222 store i128 %or, i128* @v128, align 16
225 ; CHECK: movq v128(%rip), %rax
229 ; CHECK-NEXT: movq %rcx, v128(%rip)
230 ; CHECK-NEXT: movq %rax, v128+8(%rip)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dfp128-i128.ll246 @v128 = common global i128 0, align 16
250 ; unsigned __int128 v128, v128_2;
252 ; v128 = ((v128 << 96) | v128_2);
262 ; CHECK-NEXT: movq %rax, v128+{{.*}}(%rip)
265 %0 = load i128, i128* @v128, align 16
269 store i128 %or, i128* @v128, align 16
/external/swiftshader/third_party/llvm-7.0/llvm/test/Assembler/
Dinvalid-datalayout22.ll3 target datalayout = "v128:0:128"
D2008-07-10-APInt.ll4 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80…
/external/llvm/test/Assembler/
Dinvalid-datalayout22.ll3 target datalayout = "v128:0:128"
D2008-07-10-APInt.ll4 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dunaligned.ll2 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f12…
4 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f12…
/external/llvm/test/CodeGen/PowerPC/
Dunaligned.ll2 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f12…
4 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f12…
Dlongdbl-truncate.ll2 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f12…
Dpr13641.ll2 … "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
/external/swiftshader/third_party/LLVM/test/Assembler/
D2008-07-10-APInt.ll3 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80…
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Dlongdbl-truncate.ll2 …i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f12…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dmodule-inline-asm.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
/external/llvm/test/CodeGen/NVPTX/
Dmodule-inline-asm.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"

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