Searched refs:v128i16 (Results 1 – 16 of 16) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 85 v128i16 = 37, //128 x i16 enumerator
279 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
341 case v128i16: return i16; in getVectorElementType()
379 case v128i16: return 128; in getVectorNumElements()
509 case v128i16: in getSizeInBits()
621 if (NumElements == 128) return MVT::v128i16; in getVectorVT()
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| D | ValueTypes.td | 62 def v128i16: ValueType<2048,37>; //128 x i16 vector value
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 103 CCIfType<[v64i32,v128i16,v256i8],
109 CCIfType<[v64i32,v128i16,v256i8],
129 CCIfType<[v64i32,v128i16,v256i8],
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| D | HexagonRegisterInfo.td | 285 [v64i16, v128i16, v64i16]>;
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| D | HexagonISelLoweringHVX.cpp | 20 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
49 addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 88 v128i16 = 40, //128 x i16 enumerator
383 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
458 case v128i16: in getVectorElementType()
527 case v128i16: return 128; in getVectorNumElements()
747 case v128i16: in getSizeInBits()
862 if (NumElements == 128) return MVT::v128i16; in getVectorVT()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 166 case MVT::v128i16: return "v128i16"; in getEVTString()
247 case MVT::v128i16: return VectorType::get(Type::getInt16Ty(Context), 128); in getTypeForEVT()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 169 case MVT::v128i16: return "v128i16"; in getEVTString()
247 case MVT::v128i16: return VectorType::get(Type::getInt16Ty(Context), 128); in getTypeForEVT()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
424 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 || in RetCC_Hexagon()
547 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1141 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { in LowerFormalArguments()
1770 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
2005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); in HexagonTargetLowering()
2897 case MVT::v128i16: in getRegForInlineAsmConstraint()
3033 case MVT::v128i16: in allowsMisalignedMemoryAccesses()
3072 case MVT::v128i16: in findRepresentativeClass()
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| D | HexagonRegisterInfo.td | 238 [v256i8,v128i16,v64i32,v32i64], 2048,
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| D | HexagonInstrInfoV60.td | 799 defm : STrivv_pats <v64i16, v128i16>;
874 defm : LDrivv_pats <v64i16, v128i16>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 64 def v128i16: ValueType<2048,40>; //128 x i16 vector value
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 97 case MVT::v128i16: return "MVT::v128i16"; in getEnumName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 105 case MVT::v128i16: return "MVT::v128i16"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 195 def llvm_v128i16_ty : LLVMType<v128i16>; //128 x i16
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 223 def llvm_v128i16_ty : LLVMType<v128i16>; //128 x i16
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