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Searched refs:v255 (Results 1 – 25 of 43) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dgfx9_asm_all.s7 ds_add_u32 v255, v2 offset:65535
10 ds_add_u32 v1, v255 offset:65535
28 ds_sub_u32 v255, v2 offset:65535
31 ds_sub_u32 v1, v255 offset:65535
49 ds_rsub_u32 v255, v2 offset:65535
52 ds_rsub_u32 v1, v255 offset:65535
70 ds_inc_u32 v255, v2 offset:65535
73 ds_inc_u32 v1, v255 offset:65535
91 ds_dec_u32 v255, v2 offset:65535
94 ds_dec_u32 v1, v255 offset:65535
[all …]
Dgfx8_asm_all.s6 ds_add_u32 v255, v2 offset:65535
9 ds_add_u32 v1, v255 offset:65535
27 ds_sub_u32 v255, v2 offset:65535
30 ds_sub_u32 v1, v255 offset:65535
48 ds_rsub_u32 v255, v2 offset:65535
51 ds_rsub_u32 v1, v255 offset:65535
69 ds_inc_u32 v255, v2 offset:65535
72 ds_inc_u32 v1, v255 offset:65535
90 ds_dec_u32 v255, v2 offset:65535
93 ds_dec_u32 v1, v255 offset:65535
[all …]
Dgfx7_asm_all.s6 ds_add_u32 v255, v2 offset:65535
9 ds_add_u32 v1, v255 offset:65535
27 ds_sub_u32 v255, v2 offset:65535
30 ds_sub_u32 v1, v255 offset:65535
48 ds_rsub_u32 v255, v2 offset:65535
51 ds_rsub_u32 v1, v255 offset:65535
69 ds_inc_u32 v255, v2 offset:65535
72 ds_inc_u32 v1, v255 offset:65535
90 ds_dec_u32 v255, v2 offset:65535
93 ds_dec_u32 v1, v255 offset:65535
[all …]
Dmimg-err.s44 image_atomic_add v[6:7], v255, s[8:15] dmask:0x2
47 image_atomic_add v[6:7], v255, s[8:15] dmask:0xf
56 image_atomic_add v[6:7], v255, s[8:15] dmask:0x2 tfe
Dvop1-gfx9.s31 v_sat_pk_u8_i16 v255, v1
43 v_screen_partition_4se_b32 v5, v255
Ddl-insts.s10 v_fmac_f32 v255, v1, v2
12 v_fmac_f32 v5, v255, v2
44 v_fmac_f32 v5, v1, v255
49 v_fmac_f32_e64 v255, v1, v2
51 v_fmac_f32_e64 v5, v255, v2
79 v_fmac_f32_e64 v5, v1, v255
130 v_fmac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
132 v_fmac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
134 v_fmac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
195 v_xnor_b32 v255, v1, v2
[all …]
Dvopc.s25 v_cmp_lt_f32 vcc, v255, v255
Dmubuf-gfx9.s60 buffer_store_format_d16_hi_x v255, off, s[12:15], s4
64 buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095
Dvop3-errs.s65 v_interp_p2_f32_e64 v255, v2, attr0.x high
68 v_interp_p2_f32_e64 v255, v2, attr0.x v0
Dds.s18 ds_add_src2_f32 v255 offset:65535
258 ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255
467 ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255
Dvop3p-err.s79 v_pk_add_f16 v255, s1, s2
Ddl-insts-err.s383 v_dot2_f32_f16 v255, s1, s2, s3
385 v_dot2_i32_i16 v255, s1, s2, s3
387 v_dot2_u32_u16 v255, s1, s2, s3
Dvop3.s415 v_cmpx_class_f16_e64 s[10:11], v255, s2
647 v_interp_p2_f32_e64 v255, v2, attr0.x
/external/llvm/test/MC/AMDGPU/
Dvopc.s25 v_cmp_lt_f32 vcc, v255, v255
/external/webp/src/dsp/
Dupsampling_neon.c82 #define v255 vdup_n_u8(255) macro
98 INIT_VECTOR4(r_g_b_v255, r, g, b, v255); \
104 INIT_VECTOR4(b_g_r_v255, b, g, r, v255); \
110 INIT_VECTOR4(v255_r_g_b, v255, r, g, b); \
122 const uint8x8_t ba = vsri_n_u8(b, v255, 4); /* shift a, insert b */ \
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvopc_vi.txt12 # VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
Dmov.txt24 # CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvopc_vi.txt12 # VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
Dvop1_gfx9.txt6 # GFX9: v_cvt_norm_i16_f16_e32 v255, v1 ; encoding: [0x01,0x9b,0xfe,0x7f]
18 # GFX9: v_sat_pk_u8_i16_e32 v5, v255 ; encoding: [0xff,0x9f,0x0a,0x7e]
Dexp_vi.txt36 # VI: exp null v255, v0, v255, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0xff,0x00,0xff,0x00]
Dgfx9_dasm_all.txt6 # CHECK: ds_add_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
9 # CHECK: ds_add_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
24 # CHECK: ds_sub_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00]
27 # CHECK: ds_sub_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00]
42 # CHECK: ds_rsub_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
45 # CHECK: ds_rsub_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
60 # CHECK: ds_inc_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
63 # CHECK: ds_inc_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
78 # CHECK: ds_dec_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
81 # CHECK: ds_dec_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
[all …]
Dgfx8_dasm_all.txt6 # CHECK: ds_add_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
9 # CHECK: ds_add_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
24 # CHECK: ds_sub_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00]
27 # CHECK: ds_sub_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00]
42 # CHECK: ds_rsub_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
45 # CHECK: ds_rsub_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
60 # CHECK: ds_inc_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
63 # CHECK: ds_inc_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
78 # CHECK: ds_dec_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
81 # CHECK: ds_dec_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
[all …]
Dvop3_gfx9.txt195 # GFX9: v_mad_mix_f32 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
198 # GFX9: v_mad_mix_f32 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04]
231 # GFX9: v_mad_mix_f32 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04]
261 # GFX9: v_mad_mix_f32 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07]
345 # GFX9: v_mad_mixhi_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
348 # GFX9: v_mad_mixhi_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]
378 # GFX9: v_mad_mixhi_f16 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04]
408 # GFX9: v_mad_mixhi_f16 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07]
492 # GFX9: v_mad_mixlo_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
495 # GFX9: v_mad_mixlo_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04]
[all …]
Dmov.txt24 # CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]
Ddl-insts.txt6 # CHECK: v_fmac_f32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x77]
9 # CHECK: v_fmac_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x76]
57 # CHECK: v_fmac_f32_e32 v5, v1, v255 ; encoding: [0x01,0xff,0x0b,0x76]
63 # CHECK: v_fmac_f32_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x3b,0xd1,0x01,0x05,0x02,0x00]
66 # CHECK: v_fmac_f32_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x3b,0xd1,0xff,0x05,0x02,0x00]
108 # CHECK: v_fmac_f32_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x3b,0xd1,0x01,0xff,0x03,0x00]
183 # CHECK: v_fmac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0…
186 # CHECK: v_fmac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0…
189 # CHECK: v_fmac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0…
279 # CHECK: v_xnor_b32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x7b]
[all …]

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