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Searched refs:v4i1 (Results 1 – 25 of 73) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td231 [(set v4f64:$FRT, (vselect v4i1:$FRA,
237 [(set v4f32:$FRT, (vselect v4i1:$FRA,
243 [(set v4i1:$FRT, (vselect v4i1:$FRA,
244 v4i1:$FRC, v4i1:$FRB))]>;
271 [(set v4i1:$dst,
272 (select i1:$cond, v4i1:$T, v4i1:$F))]>;
349 [/* (set v4i1:$FRT, v4i1:$FRB) */]>;
405 [(set v4i1:$FRT,
406 (PPCqvaligni v4i1:$FRA, v4i1:$FRB,
424 [(set v4i1:$FRT,
[all …]
DPPCCallingConv.td63 CCIfType<[v4f64, v4f32, v4i1],
119 CCIfType<[v4f64, v4f32, v4i1],
169 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
186 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td231 [(set v4f64:$FRT, (vselect v4i1:$FRA,
237 [(set v4f32:$FRT, (vselect v4i1:$FRA,
243 [(set v4i1:$FRT, (vselect v4i1:$FRA,
244 v4i1:$FRC, v4i1:$FRB))]>;
271 [(set v4i1:$dst,
272 (select i1:$cond, v4i1:$T, v4i1:$F))]>;
349 [/* (set v4i1:$FRT, v4i1:$FRB) */]>;
405 [(set v4i1:$FRT,
406 (PPCqvaligni v4i1:$FRA, v4i1:$FRB,
424 [(set v4i1:$FRT,
[all …]
DPPCCallingConv.td64 CCIfType<[v4f64, v4f32, v4i1],
101 CCIfType<[v4f64, v4f32, v4i1],
158 CCIfType<[v4f64, v4f32, v4i1],
221 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
239 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
/external/swiftshader/third_party/subzero/crosstest/
Dtest_select_main.cpp70 void testSelect<v4f32, v4i1>(size_t &TotalTests, size_t &Passes, in testSelect()
96 std::cout << vectAsString<v4i1>(Cond) in testSelect()
140 testSelect<v4f32, v4i1>(TotalTests, Passes, Failures); in main()
141 testSelect<v4si32, v4i1>(TotalTests, Passes, Failures); in main()
142 testSelect<v4ui32, v4i1>(TotalTests, Passes, Failures); in main()
147 testSelectI1<v4i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops_main.cpp173 testInsertElement<v4i1>(TotalTests, Passes, Failures); in main()
184 testExtractElement<v4i1>(TotalTests, Passes, Failures); in main()
195 testShuffleVector<v4i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops.def29 X(v4i1, v4ui32, 4) \
Dvectors.def30 X(v4i1, v4si32, 4) \
/external/swiftshader/third_party/subzero/src/
DIceTypes.def47 X(v4i1, 4, 1, 4, i1, "<4 x i1>", "v4i1") \
75 X(v4i1, 1, 1, 0, 0, 1, 1, v4i1) \
80 X(v4i32, 1, 1, 0, 1, 0, 1, v4i1) \
81 X(v4f32, 1, 0, 1, 0, 0, 1, v4i1) \
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h60 v4i1 = 14, // 4 x i1 enumerator
318 case v4i1: in getVectorElementType()
403 case v4i1: in getVectorNumElements()
450 case v4i1: return 4; in getSizeInBits()
594 if (NumElements == 4) return MVT::v4i1; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h62 v4i1 = 16, // 4 x i1 enumerator
422 case v4i1: in getVectorElementType()
570 case v4i1: in getVectorNumElements()
648 case v4i1: in getSizeInBits()
834 if (NumElements == 4) return MVT::v4i1; in getVectorVT()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td15 def V4I1: PatLeaf<(v4i1 PredRegs:$R)>;
231 def: vcmp_vi1_pat<A2_vcmpheq, seteq, V4I16, v4i1>;
232 def: vcmp_vi1_pat<A2_vcmphgt, setgt, V4I16, v4i1>;
233 def: vcmp_vi1_pat<A2_vcmphgtu, setugt, V4I16, v4i1>;
309 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, v4i1>;
316 def: InvertCmp_pat<A2_vcmphgtu, setult, V4I16, v4i1>;
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp617 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
618 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
648 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, in getCastInstrCost()
649 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, in getCastInstrCost()
673 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
674 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
686 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, in getCastInstrCost()
687 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, in getCastInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp142 case MVT::v4i1: return "v4i1"; in getEVTString()
223 case MVT::v4i1: return VectorType::get(Type::getInt1Ty(Context), 4); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp146 case MVT::v4i1: return "v4i1"; in getEVTString()
224 case MVT::v4i1: return VectorType::get(Type::getInt1Ty(Context), 4); in getTypeForEVT()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp138 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
139 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
301 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td324 def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>;
419 (v4i1 VK4:$mask), (iPTR 0))),
445 (v4i1 VK4:$mask), (iPTR 0))),
495 (v4i1 VK4:$mask), (iPTR 0))),
508 (v4i1 VK4:$mask), (iPTR 0))),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp199 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
200 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
362 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
/external/llvm/test/CodeGen/X86/
Dsse1.ll37 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-16.ll32 ; Test a v4i1->v4i32 extension.
Dvec-move-15.ll32 ; Test a v4i1->v4i32 extension.
Dvec-move-17.ll32 ; Test a v4i32->v4i1 truncation.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-move-15.ll32 ; Test a v4i1->v4i32 extension.
Dvec-move-16.ll32 ; Test a v4i1->v4i32 extension.
Dvec-and-03.ll38 ; Test a v4i1->v4i32 extension.

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