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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfast-isel-ext.ll1 … -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
2 …st-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
3 …fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
16 ; v7-LABEL: zext_1_8:
17 ; v7: and r0, r0, #1
23 ; v7-LABEL: zext_1_16:
24 ; v7: and r0, r0, #1
30 ; v7-LABEL: zext_1_32:
31 ; v7: and r0, r0, #1
37 ; v7-LABEL: zext_8_16:
[all …]
/external/llvm/test/CodeGen/ARM/
Dfast-isel-ext.ll1 … -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
2 …st-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
3 …fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
16 ; v7-LABEL: zext_1_8:
17 ; v7: and r0, r0, #1
23 ; v7-LABEL: zext_1_16:
24 ; v7: and r0, r0, #1
30 ; v7-LABEL: zext_1_32:
31 ; v7: and r0, r0, #1
37 ; v7-LABEL: zext_8_16:
[all …]
/external/llvm/test/MC/AArch64/
Dneon-compare-instructions.s12 cmeq v5.8h, v6.8h, v7.8h
14 cmeq v9.4s, v7.4s, v8.4s
34 cmhs v5.8h, v6.8h, v7.8h
36 cmhs v9.4s, v7.4s, v8.4s
42 cmls v5.8h, v7.8h, v6.8h
44 cmls v9.4s, v8.4s, v7.4s
71 cmge v5.8h, v6.8h, v7.8h
73 cmge v9.4s, v7.4s, v8.4s
79 cmle v5.8h, v7.8h, v6.8h
81 cmle v9.4s, v8.4s, v7.4s
[all …]
Darm64-simd-ldst.s12 ld1.8b {v7, v8, v9, v10}, [x4]
90 st1.2d {v7, v8}, [x10]
103 ; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c]
182 ; CHECK: st1.2d { v7, v8 }, [x10] ; encoding: [0x47,0xad,0x00,0x4c]
237 ld3.2d {v7, v8, v9}, [x9]
252 st3.4s {v7, v8, v9}, [x29]
270 ; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
285 ; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
289 ld4.8b {v4, v5, v6, v7}, [x19]
290 ld4.16b {v4, v5, v6, v7}, [x19]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-compare-instructions.s12 cmeq v5.8h, v6.8h, v7.8h
14 cmeq v9.4s, v7.4s, v8.4s
34 cmhs v5.8h, v6.8h, v7.8h
36 cmhs v9.4s, v7.4s, v8.4s
42 cmls v5.8h, v7.8h, v6.8h
44 cmls v9.4s, v8.4s, v7.4s
71 cmge v5.8h, v6.8h, v7.8h
73 cmge v9.4s, v7.4s, v8.4s
79 cmle v5.8h, v7.8h, v6.8h
81 cmle v9.4s, v8.4s, v7.4s
[all …]
Darm64-simd-ldst.s12 ld1.8b {v7, v8, v9, v10}, [x4]
90 st1.2d {v7, v8}, [x10]
103 ; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c]
182 ; CHECK: st1.2d { v7, v8 }, [x10] ; encoding: [0x47,0xad,0x00,0x4c]
237 ld3.2d {v7, v8, v9}, [x9]
252 st3.4s {v7, v8, v9}, [x29]
270 ; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
285 ; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
289 ld4.8b {v4, v5, v6, v7}, [x19]
290 ld4.16b {v4, v5, v6, v7}, [x19]
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-compare-instructions.s.cs5 0xc5,0x8c,0x67,0x6e = cmeq v5.8h, v6.8h, v7.8h
7 0xe9,0x8c,0xa8,0x6e = cmeq v9.4s, v7.4s, v8.4s
12 0xc5,0x3c,0x67,0x6e = cmhs v5.8h, v6.8h, v7.8h
14 0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s
19 0xc5,0x3c,0x67,0x6e = cmhs v5.8h, v6.8h, v7.8h
21 0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s
26 0xc5,0x3c,0x67,0x4e = cmge v5.8h, v6.8h, v7.8h
28 0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s
33 0xc5,0x3c,0x67,0x4e = cmge v5.8h, v6.8h, v7.8h
35 0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Ddeprecated-v8.s12 @ CHECK-ARMV8: warning: deprecated since v7, use 'isb'
13 @ CHECK-THUMBV8: warning: deprecated since v7, use 'isb'
14 @ CHECK-ARMV7: warning: deprecated since v7, use 'isb'
15 @ CHECK-THUMBV7: warning: deprecated since v7, use 'isb'
16 @ CHECK-ARMV6-NOT: warning: deprecated since v7, use 'isb'
18 @ CHECK-ARMV8: warning: deprecated since v7, use 'dsb'
19 @ CHECK-THUMBV8: warning: deprecated since v7, use 'dsb'
20 @ CHECK-ARMV7: warning: deprecated since v7, use 'dsb'
21 @ CHECK-THUMBV7: warning: deprecated since v7, use 'dsb'
22 @ CHECK-ARMV6-NOT: warning: deprecated since v7, use 'dsb'
[all …]
/external/llvm/test/MC/ARM/
Ddeprecated-v8.s12 @ CHECK-ARMV8: warning: deprecated since v7, use 'isb'
13 @ CHECK-THUMBV8: warning: deprecated since v7, use 'isb'
14 @ CHECK-ARMV7: warning: deprecated since v7, use 'isb'
15 @ CHECK-THUMBV7: warning: deprecated since v7, use 'isb'
16 @ CHECK-ARMV6-NOT: warning: deprecated since v7, use 'isb'
18 @ CHECK-ARMV8: warning: deprecated since v7, use 'dsb'
19 @ CHECK-THUMBV8: warning: deprecated since v7, use 'dsb'
20 @ CHECK-ARMV7: warning: deprecated since v7, use 'dsb'
21 @ CHECK-THUMBV7: warning: deprecated since v7, use 'dsb'
22 @ CHECK-ARMV6-NOT: warning: deprecated since v7, use 'dsb'
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_inv_dit_fft_8pt.s45 LD1 {v7.s}[0], [x0], x5
47 LD1 {v7.s}[1], [x0], x5
61 SQADD v11.2s, v3.2s, v7.2s //a10_v = vqadd_s32(y4_6,y12_14);
66 SQSUB v2.2s, v3.2s, v7.2s //a2_v = vqsub_s32(y4_6,y12_14);
70 SQADD v7.2s, v10.2s, v12.2s //x1_9 = vqadd_s32(a20_v,a30_v);
80 UZP1 v1.2s, v3.2s, v7.2s //x0_1 = vuzp1_s32(x0_8,x1_9);
81 UZP2 v5.2s, v3.2s, v7.2s //x8_9 = vuzp2_s32(x0_8,x1_9);
84 UZP2 v7.2s, v4.2s, v8.2s //x12_13 = vuzp2_s32(x4_12,x5_13);
85 REV64 v7.2s, v7.2s //x13_12 = vrev64_s32(x12_13);
90 SQADD v12.2s, v6.2s, v7.2s //real_imag4 = vqadd_s32(x4_5,x13_12);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dmul64-sext.ll13 %v7 = mul nsw i64 %v6, %v4
14 ret i64 %v7
27 %v7 = mul nsw i64 %v6, %v4
28 ret i64 %v7
41 %v7 = mul nsw i64 %v6, %v4
42 ret i64 %v7
55 %v7 = mul nsw i64 %v3, %v6
56 ret i64 %v7
68 %v7 = ashr exact i64 %v6, 32
69 %v8 = mul nsw i64 %v7, %v5
[all …]
DPR33749.ll18 %v7 = phi i32 [ %v29, %b28 ], [ %v5, %b1 ]
19 %v8 = mul nsw i32 %v4, %v7
20 %v9 = add nsw i32 %v8, %v7
21 %v10 = mul i32 %v7, %v7
24 %v13 = mul nsw i32 %v12, %v7
25 %v14 = add nsw i32 %v13, %v7
29 %v18 = mul i32 %v10, %v7
35 %v24 = sub nsw i32 %v7, %v23
37 %v26 = sub i32 0, %v7
42 %v29 = add nsw i32 %v3, %v7
/external/libhevc/common/arm64/
Dihevc_inter_pred_chroma_vert_w16out.s192 dup v7.2s, v6.s[1]
193 ld1 {v7.s}[1],[x6],x2 //loads pu1_src_tmp
194 umull v4.8h, v7.8b, v1.8b //vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1)
195 dup v7.2s, v7.s[1]
196 ld1 {v7.s}[1],[x6],x2
198 umlal v4.8h, v7.8b, v2.8b
199 dup v7.2s, v7.s[1]
200 ld1 {v7.s}[1],[x6]
202 umlsl v4.8h, v7.8b, v3.8b
239 ld1 {v7.8b},[x6],x2 //load and increment
[all …]
Dihevc_inter_pred_chroma_vert.s191 dup v7.2s, v6.s[1]
192 ld1 {v7.s}[1],[x6],x2 //loads pu1_src_tmp
193 umull v4.8h, v7.8b, v1.8b //vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1)
194 dup v7.2s, v7.s[1]
195 ld1 {v7.s}[1],[x6],x2
197 umlal v4.8h, v7.8b, v2.8b
198 dup v7.2s, v7.s[1]
199 ld1 {v7.s}[1],[x6]
201 umlsl v4.8h, v7.8b, v3.8b
238 ld1 {v7.8b},[x6],x2 //load and increment
[all …]
Dihevc_intra_pred_luma_planar.s148 …mov v7.8b, v5.8b //mov #1 to d7 to used for inc for row+1 and dec for nt-1-…
196 add v5.8b, v5.8b , v7.8b //(1)
198 sub v6.8b, v6.8b , v7.8b //(1)
211 add v5.8b, v5.8b , v7.8b //(2)
212 sub v6.8b, v6.8b , v7.8b //(2)
228 add v5.8b, v5.8b , v7.8b //(3)
229 sub v6.8b, v6.8b , v7.8b //(3)
245 add v5.8b, v5.8b , v7.8b //(4)
246 sub v6.8b, v6.8b , v7.8b //(4)
261 add v5.8b, v5.8b , v7.8b //(5)
[all …]
Dihevc_weighted_pred_uni.s187 … smull v7.4s, v3.4h, v0.h[0] //vmull_n_s16(pi2_src_val1, (int16_t) wgt0) iii iteration
190 add v7.4s, v7.4s , v30.4s //vaddq_s32(i4_tmp1_t, tmp_lvl_shift_t) iii iteration
199 sshl v7.4s,v7.4s,v28.4s
206 sqxtun v7.4h, v7.4s //vqmovun_s32(sto_res_tmp1) iii iteration
216 uqxtn v7.8b, v7.8h //vqmovn_u16(sto_res_tmp3) iii iteration
220 st1 {v7.s}[0],[x6],x3 //store pu1_dst i iteration iii iteration
Dihevc_inter_pred_filters_luma_vert_w16out.s130 ld1 {v7.8b},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
135 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)//
159 umlal v20.8h, v7.8b, v28.8b //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
173 umlsl v21.8h, v7.8b, v27.8b
188 umlal v30.8h, v7.8b, v26.8b
195 ld1 {v7.8b},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
230 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)//
253 umlal v20.8h, v7.8b, v28.8b //mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)//
277 umlsl v21.8h, v7.8b, v27.8b
299 umlal v30.8h, v7.8b, v26.8b
[all …]
Dihevc_itrans_recon_4x4.s149 saddl v7.4s, v0.4h, v2.4h //pi2_src[0] + pi2_src[2]
151 shl v7.4s, v7.4s,#6 //e[0] = 64*(pi2_src[0] + pi2_src[2])
154 add v19.4s, v7.4s , v6.4s //((e[0] + o[0] )
157 sub v20.4s, v7.4s , v6.4s //((e[0] - o[0])
183 saddl v7.4s, v0.4h, v2.4h //pi2_src[0] + pi2_src[2]
185 shl v7.4s, v7.4s,#6 //e[0] = 64*(pi2_src[0] + pi2_src[2])
189 add v19.4s, v7.4s , v6.4s //((e[0] + o[0] )
192 sub v20.4s, v7.4s , v6.4s //((e[0] - o[0])
/external/llvm/test/MC/Hexagon/
Dv60-alu.s56 #CHECK: 1c67d816 { v22.ub = vsub(v24.ub,{{ *}}v7.ub):sat }
57 v22.ub=vsub(v24.ub,v7.ub):sat
68 #CHECK: 1c4dc78b { v11.w = vadd(v7.w,{{ *}}v13.w):sat }
69 v11.w=vadd(v7.w,v13.w):sat
71 #CHECK: 1c48c7a4 { v4.b = vsub(v7.b,{{ *}}v8.b) }
72 v4.b=vsub(v7.b,v8.b)
80 #CHECK: 1c7ad4a6 { v7:6.h = vadd(v21:20.h,{{ *}}v27:26.h) }
81 v7:6.h=vadd(v21:20.h,v27:26.h)
83 #CHECK: 1cc7c564 { v4.uw = vabsdiff(v5.w,{{ *}}v7.w) }
84 v4.uw=vabsdiff(v5.w,v7.w)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dv60-alu.s56 #CHECK: 1c67d816 { v22.ub = vsub(v24.ub,{{ *}}v7.ub):sat }
57 v22.ub=vsub(v24.ub,v7.ub):sat
68 #CHECK: 1c4dc78b { v11.w = vadd(v7.w,{{ *}}v13.w):sat }
69 v11.w=vadd(v7.w,v13.w):sat
71 #CHECK: 1c48c7a4 { v4.b = vsub(v7.b,{{ *}}v8.b) }
72 v4.b=vsub(v7.b,v8.b)
80 #CHECK: 1c7ad4a6 { v7:6.h = vadd(v21:20.h,{{ *}}v27:26.h) }
81 v7:6.h=vadd(v21:20.h,v27:26.h)
83 #CHECK: 1cc7c564 { v4.uw = vabsdiff(v5.w,{{ *}}v7.w) }
84 v4.uw=vabsdiff(v5.w,v7.w)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvintrp.txt3 #VI: v_interp_p1_f32_e32 v7, v212, attr16.y
6 #VI: v_interp_p2_f32_e32 v7, v212, attr16.y
9 #VI: v_interp_mov_f32_e32 v7, invalid_param_212, attr16.y
12 #VI: v_interp_mov_f32_e32 v7, p10, attr16.y
15 #VI: v_interp_mov_f32_e32 v7, p20, attr16.y
18 #VI: v_interp_mov_f32_e32 v7, p0, attr16.y
21 #VI: v_interp_mov_f32_e32 v7, invalid_param_3, attr16.y
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s177 add v7.4h, v1.4h, v9.4h // x3 = d1 + (d3 >> 1)//
181 add v10.4h, v4.4h , v7.4h // x0+x3
184 sub v13.4h, v4.4h , v7.4h
194 trn2 v7.4h, v12.4h, v13.4h
197 trn1 v11.2s, v5.2s, v7.2s // 8
199 trn2 v13.2s, v5.2s, v7.2s
367 add v7.4h, v1.4h, v9.4h // x3 = d1 + (d3 >> 1)//
370 add v10.4h, v4.4h , v7.4h // x0+x3
373 sub v13.4h, v4.4h , v7.4h
385 trn2 v7.4h, v12.4h, v13.4h
[all …]
Dih264_deblk_chroma_av8.s94 ld2 {v6.8b, v7.8b}, [x0], x1 //D6 = p1u , D7 = p1v
102 uaddl v10.8h, v7.8b, v1.8b //Q4,Q5 = q0 + p1
108 mov v6.d[1], v7.d[0]
120 umlal v28.8h, v7.8b, v31.8b //Q14,Q7 = (X2(p1U) + p0U + q1U)
203 ld4 {v4.h, v5.h, v6.h, v7.h}[0], [x0], x1
204 ld4 {v4.h, v5.h, v6.h, v7.h}[1], [x0], x1
205 ld4 {v4.h, v5.h, v6.h, v7.h}[2], [x0], x1
206 ld4 {v4.h, v5.h, v6.h, v7.h}[3], [x0], x1
224 mov v6.d[1], v7.d[0]
230 uaddl v16.8h, v3.8b, v7.8b //(p0 + q1)
[all …]
Dih264_ihadamard_scaling_av8.s112 ssubl v7.4s, v0.4h, v3.4h //x3 = x4 - x7
115 add v1.4s, v7.4s, v6.4s //pi4_tmp_ptr[1] = x3 + x2
117 sub v3.4s, v7.4s, v6.4s //pi4_tmp_ptr[3] = x3 - x2
126 trn2 v7.4s, v2.4s, v3.4s
130 trn1 v1.2d, v5.2d, v7.2d
131 trn2 v3.2d, v5.2d, v7.2d
137 sub v7.4s, v0.4s, v3.4s //x3 = x4-x7
140 add v1.4s, v7.4s, v6.4s //pi4_tmp_ptr[1] = x3 + x2
142 sub v3.4s, v7.4s, v6.4s //pi4_tmp_ptr[3] = x3 - x2
/external/bcc/src/cc/vendor/
Dtinyformat.hpp430 …_7 const T1& v1, const T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7
431 …1, const T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8
432 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
433 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
434 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
435 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
436 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
437 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
438 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
439 … T2& v2, const T3& v3, const T4& v4, const T5& v5, const T6& v6, const T7& v7, const T8& v8, const…
[all …]

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