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Searched refs:v_and_b32_e32 (Results 1 – 25 of 105) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dliterals.s125 v_and_b32_e32 v0, 0.5, v1 label
137 v_and_b32_e32 v0, -1.0, v1 label
149 v_and_b32_e32 v0, 4.0, v1 label
161 v_and_b32_e32 v0, 0.0, v1 label
173 v_and_b32_e32 v0, 1.5, v1 label
181 v_and_b32_e32 v0, -3.1415, v1 label
189 v_and_b32_e32 v0, 100000000000000000000000.0, v1 label
197 v_and_b32_e32 v0, 10000000.0, v1 label
205 v_and_b32_e32 v0, 3.402823e+38, v1 label
213 v_and_b32_e32 v0, 2.3509886e-38, v1 label
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dand.ll11 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
12 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
29 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
30 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
31 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
32 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
95 ; SI: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
111 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
125 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
137 ; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
[all …]
Dtrunc-cmp-constant.ll6 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
21 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
47 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
59 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
83 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
95 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
118 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
134 ; XSI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
Dlower-range-metadata-intrinsic-call.ll17 ; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x1ff, v0
29 ; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xff, v0
Dudivrem.ll44 ; SI: v_and_b32_e32 [[Tmp1:v[0-9]+]]
128 ; SI-DAG: v_and_b32_e32
151 ; SI-DAG: v_and_b32_e32
278 ; SI-DAG: v_and_b32_e32
301 ; SI-DAG: v_and_b32_e32
324 ; SI-DAG: v_and_b32_e32
Dudiv.ll97 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xff, v{{[0-9]+}}
111 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xffff, v{{[0-9]+}}
125 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x7fffff, v{{[0-9]+}}
Dtrunc.ll53 ; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
87 ; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dextend-bit-ops-i16.ll4 ; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
5 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
20 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
35 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
Dmul_uint24-amdgcn.ll54 ; SI: v_and_b32_e32
68 ; SI: v_and_b32_e32
188 ; GCN-DAG: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
208 ; GCN-NEXT: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
231 ; GCN: v_and_b32_e32 v0, 0x1fffe, v0
248 ; GCN-DAG: v_and_b32_e32 v0, [[U23_MASK]], v0
249 ; GCN-DAG: v_and_b32_e32 v1, [[U23_MASK]], v1
252 ; GCN: v_and_b32_e32 v1, s6, v1
253 ; GCN: v_and_b32_e32 v0, 0x7ffffe, v0
255 ; GCN: v_and_b32_e32 v0, 0x1fffe, v0
Dtrunc-cmp-constant.ll8 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
23 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
49 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
61 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
85 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
97 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
120 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
136 ; XSI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
Dand.ll97 ; SI: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
113 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
127 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
139 ; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
150 ; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}}
161 ; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}}
265 ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, {{v[0-9]+}}
266 ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}}
282 ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]]
283 ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]]
[all …]
Dinsert_vector_elt.v2i16.ll212 ; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]]
235 ; CIVI-DAG: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]]
259 ; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]]
284 ; GFX9-DAG: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
287 ; CI: v_and_b32_e32 [[AND:v[0-9]+]], 0xffff, [[VEC]]
306 ; CI: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
307 ; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
326 ; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]]
348 ; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]]
370 ; GFX9-DAG: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
[all …]
Dextract-lowbits.ll118 ; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
120 ; SI-NEXT: v_and_b32_e32 v0, v1, v0
129 ; VI-NEXT: v_and_b32_e32 v0, v1, v0
171 ; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
180 ; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
Dmove-to-valu-worklist.ll12 ; GCN: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
13 ; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
Dllvm.amdgcn.image.d16.dim.ll63 ; UNPACKED: v_and_b32_e32
75 ; UNPACKED: v_and_b32_e32
77 ; UNPACKED: v_and_b32_e32
89 ; UNPACKED: v_and_b32_e32
91 ; UNPACKED: v_and_b32_e32
Dllvm.log10.f16.ll54 ; SI-NOT: v_and_b32_e32
56 ; VI-NOT: v_and_b32_e32
58 ; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
Dllvm.log.f16.ll54 ; SI-NOT: v_and_b32_e32
56 ; VI-NOT: v_and_b32_e32
58 ; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
Dpartial-shift-shrink.ll106 ; GCN-NEXT: v_and_b32_e32 v1, 15, v2
118 ; GCN-NEXT: v_and_b32_e32 v2, 16, v2
130 ; GCN-NEXT: v_and_b32_e32 v2, 31, v2
Dpack.v2f16.ll62 ; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VAL0]]
87 ; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VAL0]]
155 ; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
177 ; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL]]
198 ; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL]]
Dtrunc.ll59 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
69 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
112 ; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
Dbfe-combine.ll11 ; CI: v_and_b32_e32 v[[ADDRLO:[0-9]+]], 0x3fc, v[[SHR]]
34 ; CI: v_and_b32_e32 v[[AND:[0-9]+]], 0x7fff8000, v[[SHR]]
Danyext.ll24 ; GFX89: v_and_b32_e32 [[AND:v[0-9]+]], 1, [[XOR]]
45 ; GFX9: v_and_b32_e32 v{{[0-9]+}}, 0x80008000
Dselect-fabs-fneg-extract.ll56 ; GCN-DAG: v_and_b32_e32 [[X_ABS:v[0-9]+]], 0x7fffffff, [[X]]
104 ; GCN: v_and_b32_e32 [[X_ABS:v[0-9]+]], 0x7fffffff, [[X]]
123 ; GCN: v_and_b32_e32 [[FABS_X:v[0-9]+]], 0x7fffffff, [[X]]
171 ; GCN-DAG: v_and_b32_e32 [[FABS_X:v[0-9]+]], 0x7fffffff, [[X]]
191 ; GCN-DAG: v_and_b32_e32 [[FABS_X:v[0-9]+]], 0x7fffffff, [[X]]
518 ; GCN-DAG: v_and_b32_e32 [[Y_ABS:v[0-9]+]], 0x7fffffff, [[Y]]
541 ; GCN-DAG: v_and_b32_e32 [[X_ABS:v[0-9]+]], 0x7fffffff, [[X]]
564 ; GCN-DAG: v_and_b32_e32 [[Y_ABS:v[0-9]+]], 0x7fffffff, [[Y]]
585 ; GCN-DAG: v_and_b32_e32 [[X_ABS:v[0-9]+]], 0x7fffffff, [[X]]
607 ; GCN-DAG: v_and_b32_e32 [[Y_ABS:v[0-9]+]], 0x7fffffff, [[Y]]
[all …]
Dmul.i16.ll7 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[K]]
8 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[K]]
Dfabs.f16.ll78 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7fff7fff, [[VAL]]
117 ; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]]
144 ; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]]
182 ; GCN: v_and_b32_e32 [[AND:v[0-9]+]], 0x7fff7fff, [[VAL]]

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