Searched refs:v_lshl_b32_e32 (Results 1 – 11 of 11) sorted by relevance
/external/llvm/test/CodeGen/AMDGPU/ |
D | shl.ll | 13 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 14 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 36 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 37 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 38 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 39 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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D | commute-shifts.ll | 5 ; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | shl.ll | 15 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 16 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 38 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 39 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 41 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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D | commute-shifts.ll | 5 ; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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D | bfe-patterns.ll | 27 ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]] 103 ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
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D | extract-lowbits.ll | 172 ; SI-NEXT: v_lshl_b32_e32 v0, v0, v1
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D | shl.v2i16.ll | 53 ; CI: v_lshl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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D | insert_vector_elt.v2i16.ll | 458 ; CI-DAG: v_lshl_b32_e32 [[MASK:v[0-9]+]], 0xffff, [[SCALED_IDX]] 486 ; CI-DAG: v_lshl_b32_e32 [[MASK:v[0-9]+]], 0xffff, [[SCALED_IDX]]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
D | vop3-convert.s | 272 v_lshl_b32_e32 v1, v2, v3 label
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D | vop2.s | 227 v_lshl_b32_e32 v1, v2, v3 label
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/external/llvm/test/MC/AMDGPU/ |
D | vop2.s | 219 v_lshl_b32_e32 v1, v2, v3 label
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