Searched refs:v_max_i32_e32 (Results 1 – 13 of 13) sorted by relevance
/external/llvm/test/CodeGen/AMDGPU/ |
D | sminmax.ll | 21 ; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG]], [[SRC]] 60 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]] 61 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]] 121 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]] 122 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]] 123 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]] 124 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG3]], [[SRC3]] 174 ; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]]
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D | max.ll | 6 ; SI: v_max_i32_e32 19 ; SI: v_max_i32_e32 20 ; SI: v_max_i32_e32 21 ; SI: v_max_i32_e32 22 ; SI: v_max_i32_e32 63 ; SI: v_max_i32_e32 100 ; SI: v_max_i32_e32
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D | smed3.ll | 45 ; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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D | umed3.ll | 64 ; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | sminmax.ll | 24 ; GCN: v_max_i32_e32 {{v[0-9]+}}, [[SRC]], [[NEG]] 43 ; GCN: v_max_i32_e32 [[MAX:v[0-9]+]], [[SRC]], [[NEG]] 83 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]] 84 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]] 153 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]] 154 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]] 155 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC2]], [[NEG2]] 156 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC3]], [[NEG3]] 211 ; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]]
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D | max.ll | 6 ; SI: v_max_i32_e32 19 ; SI: v_max_i32_e32 20 ; SI: v_max_i32_e32 21 ; SI: v_max_i32_e32 22 ; SI: v_max_i32_e32 63 ; SI: v_max_i32_e32 100 ; SI: v_max_i32_e32
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D | smed3.ll | 46 ; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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D | umed3.ll | 65 ; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
D | vop2.s | 196 v_max_i32_e32 v1, v2, v3 label
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop2_vi.txt | 48 # VI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop2_vi.txt | 48 # VI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
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D | gfx8_dasm_all.txt | 33429 # CHECK: v_max_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x1a] 33432 # CHECK: v_max_i32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x1b] 33435 # CHECK: v_max_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x1a] 33438 # CHECK: v_max_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x1a] 33441 # CHECK: v_max_i32_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x1a] 33444 # CHECK: v_max_i32_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x1a] 33447 # CHECK: v_max_i32_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x1a] 33450 # CHECK: v_max_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x1a] 33453 # CHECK: v_max_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x1a] 33456 # CHECK: v_max_i32_e32 v5, tba_lo, v2 ; encoding: [0x6c,0x04,0x0a,0x1a] [all …]
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D | gfx9_dasm_all.txt | 28881 # CHECK: v_max_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x1a] 28884 # CHECK: v_max_i32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x1b] 28887 # CHECK: v_max_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x1a] 28890 # CHECK: v_max_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x1a] 28893 # CHECK: v_max_i32_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x1a] 28896 # CHECK: v_max_i32_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x1a] 28899 # CHECK: v_max_i32_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x1a] 28902 # CHECK: v_max_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x1a] 28905 # CHECK: v_max_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x1a] 28908 # CHECK: v_max_i32_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x1a] [all …]
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