Searched refs:v_mul_u32_u24_e32 (Results 1 – 11 of 11) sorted by relevance
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | mul_uint24-amdgcn.ll | 53 ; SI: v_mul_u32_u24_e32 67 ; SI: v_mul_u32_u24_e32 137 ; GCN-DAG: v_mul_u32_u24_e32 168 ; GCN: v_mul_u32_u24_e32 [[MUL24:v[0-9]+]] 186 ; GCN-DAG: v_mul_u32_u24_e32 v[[MUL_LO:[0-9]+]], 228 ; GCN-DAG: v_mul_u32_u24_e32 v0, 0xea, v0 229 ; GCN-DAG: v_mul_u32_u24_e32 v1, 0x39b, v1 230 ; GCN: v_mul_u32_u24_e32 v0, v0, v1 232 ; GCN: v_mul_u32_u24_e32 v0, 0x63, v0 250 ; GCN-DAG: v_mul_u32_u24_e32 v0, 0xea, v0 [all …]
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D | llvm.r600.read.local.size.ll | 60 ; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[X]], [[VY]] 79 ; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[X]], [[VZ]] 99 ; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[Y]], [[VZ]]
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D | sdwa-peephole.ll | 39 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v[[DST0]], v[[DST1]] 72 ; NOSDWA: v_mul_u32_u24_e32 v[[DST_MUL:[0-9]+]], v[[DST0]], v[[DST1]] 95 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 122 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 266 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 289 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 314 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 409 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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D | lshl64-to-32.ll | 48 ; GCN: v_mul_u32_u24_e32 [[M:v[0-9]+]], 7, v{{[0-9]+}}
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D | llvm.amdgcn.sendmsg.ll | 127 ; GCN: v_mul_u32_u24_e32
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/external/llvm/test/CodeGen/AMDGPU/ |
D | llvm.r600.read.local.size.ll | 60 ; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[X]], [[VY]] 79 ; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[X]], [[VZ]] 99 ; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[Y]], [[VZ]]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
D | vop2.s | 166 v_mul_u32_u24_e32 v1, v2, v3 label
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop2_vi.txt | 33 # VI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop2_vi.txt | 33 # VI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
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D | gfx8_dasm_all.txt | 32409 # CHECK: v_mul_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] 32412 # CHECK: v_mul_u32_u24_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x11] 32415 # CHECK: v_mul_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x10] 32418 # CHECK: v_mul_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x10] 32421 # CHECK: v_mul_u32_u24_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x10] 32424 # CHECK: v_mul_u32_u24_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x10] 32427 # CHECK: v_mul_u32_u24_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x10] 32430 # CHECK: v_mul_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x10] 32433 # CHECK: v_mul_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x10] 32436 # CHECK: v_mul_u32_u24_e32 v5, tba_lo, v2 ; encoding: [0x6c,0x04,0x0a,0x10] [all …]
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D | gfx9_dasm_all.txt | 28086 # CHECK: v_mul_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] 28089 # CHECK: v_mul_u32_u24_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x11] 28092 # CHECK: v_mul_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x10] 28095 # CHECK: v_mul_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x10] 28098 # CHECK: v_mul_u32_u24_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x10] 28101 # CHECK: v_mul_u32_u24_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x10] 28104 # CHECK: v_mul_u32_u24_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x10] 28107 # CHECK: v_mul_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x10] 28110 # CHECK: v_mul_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x10] 28113 # CHECK: v_mul_u32_u24_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x10] [all …]
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