| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.readfirstlane.ll | 6 ; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, v{{[0-9]+}}
15 ; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, [[VVAL]]
27 ; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, [[VVAL]]
|
| D | control-flow-fastregalloc.ll | 62 ; VMEM: v_readfirstlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC_LO]]
66 ; VMEM: v_readfirstlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC_HI]]
139 ; VMEM: v_readfirstlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC_LO]]
143 ; VMEM: v_readfirstlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC_HI]]
209 ; VMEM: v_readfirstlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC_LO]]
213 ; VMEM: v_readfirstlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC_HI]]
257 ; VMEM: v_readfirstlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC_LO]]
261 ; VMEM: v_readfirstlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC_HI]]
|
| D | missing-store.ll | 12 ; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
13 ; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
|
| D | indirect-addressing-si.ll | 123 ; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v{{[0-9]+}}
250 ; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]]
285 ; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]]
322 ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
344 ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
395 ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
415 ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
|
| D | always-uniform.ll | 8 ; GCN: v_readfirstlane_b32 s[[SCALAR:[0-9]+]], v0
|
| D | si-triv-disjoint-mem-access.ll | 89 ; GCN-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
90 ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
119 ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
120 ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
|
| D | constant-address-space-32bit.ll | 204 ; GCN: v_readfirstlane_b32
205 ; GCN-NEXT: v_readfirstlane_b32
238 ; GCN: v_readfirstlane_b32
239 ; GCN-NEXT: v_readfirstlane_b32
|
| D | llvm.amdgcn.readlane.ll | 23 ; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
|
| D | si-spill-sgpr-stack.ll | 13 ; SGPR-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
|
| D | llvm.amdgcn.writelane.ll | 25 ; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
|
| D | llvm.amdgcn.sendmsg.ll | 128 ; GCN: v_readfirstlane_b32
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | missing-store.ll | 11 ; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
12 ; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
|
| D | si-triv-disjoint-mem-access.ll | 74 ; CI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
75 ; CI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
96 ; CI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
97 ; CI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
|
| D | indirect-addressing-si.ll | 84 ; CHECK: v_readfirstlane_b32
170 ; CHECK: v_readfirstlane_b32
185 ; CHECK: v_readfirstlane_b32
213 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
226 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
269 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
283 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
|
| D | si-spill-sgpr-stack.ll | 8 ; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
|
| D | salu-to-valu.ll | 58 ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
59 ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
|
| /external/llvm/test/MC/AMDGPU/ |
| D | trap.s | 138 v_readfirstlane_b32 ttmp8, v1 label
|
| D | vop1.s | 38 v_readfirstlane_b32 s1, v2 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | trap.s | 243 v_readfirstlane_b32 ttmp8, v1 label
|
| D | vop1.s | 38 v_readfirstlane_b32 s1, v2 label
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | trap_vi.txt | 105 # VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
|
| D | vop1_vi.txt | 18 # VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | trap_vi.txt | 105 # VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
|
| D | trap_gfx9.txt | 102 # GFX9: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xe8,0x7e]
|
| D | vop1_vi.txt | 18 # VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
|